參數(shù)資料
型號(hào)： M12L64164A-7BG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 1M x 16 Bit x 4 Banks Synchronous DRAM
中文描述： 4M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝： 8 X 8 MM, LEAD FREE, VBGA-54
文件頁(yè)數(shù)： 2/45頁(yè)
文件大?。?/td> 831K
代理商： M12L64164A-7BG
ES MT
FUNCTIONAL BLOCK DIAGRAM
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
2/45
PIN FUNCTION DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A11
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
A12 , A13
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
L(U)DQM
Data Input / Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
VDD / VSS
Power Supply / Ground
Power and ground for the input buffers and the core logic.
VDDQ / VSSQ Data Output Power / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
NC
No Connection
This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ
Mode
Register
C
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
R
Bank A
Bank B
Sense Amplifier
Column Decoder
Data Control Circuit
L
I
B
Address
Clock
Generator
CLK
CKE
C
CS
RAS
CAS
WE
相關(guān)PDF資料
PDF描述
M12L64322A-5BG 512K x 32 Bit x 4 Banks Synchronous DRAM
M12L64322A-5TG 512K x 32 Bit x 4 Banks Synchronous DRAM
M12L64322A-6BG 512K x 32 Bit x 4 Banks Synchronous DRAM
M12L64322A-6TG 512K x 32 Bit x 4 Banks Synchronous DRAM
M12L64322A-7BG 512K x 32 Bit x 4 Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M12L64164A-7BG2Y 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks
M12L64164A-7BIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM
M12L64164A-7TA 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM
M12L64164A-7TG 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM
M12L64164A-7TG2Y 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks
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