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參數(shù)資料
| 型號： | M12L64164A-7BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 4M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封裝： | 8 X 8 MM, LEAD FREE, VBGA-54 |
| 文件頁數(shù)： | 15/45頁 |
| 文件大?。?/td> | 831K |
| 代理商： | M12L64164A-7BG |
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ES MT
Write command
(CS ,CAS ,
WE
= Low,RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
Read command
(CS ,CAS = Low,RAS ,
WE
= High)
Read data is available after CAS latency requirements have been met.
This command sets the burst start address given by the column address.
CBR (auto) refresh command
(CS ,RAS ,CAS = Low,
WE
, CKE = High)
This command is a request to begin the CBR refresh operation. The refresh
address is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
row activate command.
During t
RC
period (from refresh command to refresh or activate command), the
M12L64164A cannot accept any other command.
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
15/45
CLK
CLK
CKE
CKE
A12, A13
(Bank select)
A12, A13
(Bank select)
A10
A10
Add
Add
H
H
Col.
Fig. 4 Column address and
write command
Fig. 5 Column address and
read command
CLK
CKE
A12, A13
(Bank select)
A10
Add
H
Fig. 6 Auto refresh command
Col.
CS
RAS
WE
CAS
CS
RAS
WE
CAS
CS
RAS
WE
CAS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12L64322A-5BG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12L64322A-5TG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12L64322A-6BG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12L64322A-6TG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12L64322A-7BG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L64164A-7BG2Y | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks |
| M12L64164A-7BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L64164A-7TA | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L64164A-7TG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L64164A-7TG2Y | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks |
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