參數(shù)資料
型號(hào): M12L64164A-7BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VBGA-54
文件頁數(shù): 3/45頁
文件大?。?/td> 831K
代理商: M12L64164A-7BG
ES MT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Revision
:
3.0
Publication Date
:
Mar. 2007
3/45
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
UNIT
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
°
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C
°
)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
NOTE
Supply voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
Input logic high voltage
V
IH
2.0
V
DD
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.8
V
2
Output logic high voltage
V
OH
2.4
-
-
V
I
OH
= -2mA
Output logic low voltage
V
OL
-
-
0.4
V
μ
A
I
OL
= 2mA
Input leakage current
I
IL
-5
-
5
3
Output leakage current
I
OL
-5
-
5
μ
A
4
Note:
1. V
IH(max)
= 4.6V AC for pulse width
10ns acceptable.
2. V
IL(min)
= -1.5V AC for pulse width
10ns acceptable.
3. Any input 0V
V
IN
V
DD
+ 0.3V, all other pins are not under test = 0V.
4. D
out
is disabled , 0V
V
OUT
V
DD
.
CAPACITANCE
(VDD = 3.3V, TA = 25 C
, f = 1MHZ)
PARAMETER
SYMBOL
MIN
MAX
UNIT
Input capacitance (A0 ~ A11, A13 ~ A12)
C
IN1
2
4
pF
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
&
L(U)DQM)
C
IN2
2
4
pF
Data input/output capacitance (DQ0 ~ DQ15)
C
OUT
2
5
pF
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