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參數(shù)資料
| 型號： | LXT386BE |
| 英文描述： | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|四|優(yōu)稅PCM-30/E-1 |的CMOS | BGA封裝| 160PIN |塑料 |
| 文件頁數(shù)： | 41/80頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT386BE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
41
Table 12. LOS Status Monitor Register, LOS (04h)
Bit
1
Name
Function
7-0
LOS7-LOS0
Respective bit(s) are set to
“
1
”
every time the LOS processor detects a valid loss of
signal condition in transceivers 7-0.
1. On power up all register bits are set to
“
0
”
. Any change in the state causes an interrupt. All LOS interrupts
are cleared by a single read operation.
Table 13. DFM Status Monitor Register, DFM (05h)
Bit
Name
Function
1
7-0
DFM7-DFM0
Respective bit(s) are set to
“
1
”
every time the short circuit monitor detects a valid
secondary output driver short circuit condition in transceivers 7-0. Note: DFM is
available only in configurations with no transmit series resistors (T1 mode with
TVCC=3.3V).
1. On power-up all the register bits are set to
“
0
”
. All DFM interrupts are cleared by a single read operation.
Table 14. LOS Interrupt Enable Register, LIE (06h)
Bit
Name
Function
1
7-0
LIE7-LIE0
Transceiver 7-0 LOS interrupts are enabled by writing a
“
1
”
to the respective bit.
1. On power-up all the register bits are set to
“
0
”
and all interrupts are disabled.
Table 15. DFM Interrupt Enable Register, DIE (07h)
Bit
Name
Function
1
7-0
DIE7-DIE0
Transceiver 7-0 DFM interrupts are enabled by writing a
“
1
”
to the respective bit.
1. On power-up all the register bits are set to
“
0
”
and all interrupts are disabled.
Table 16. LOS Interrupt Status Register, LIS (08h)
Bit
Name
Function
1
7-0
LIS7-LIS0
These bits are set to
“
1
”
every time a LOS status change has occurred since the last
cleared interrupt in transceivers 7-0 respectively.
1. On power up all register bits are set to
“
0
”
.
Table 17. DFM Interrupt Status Register, DIS (09h)
Bit
Name
Function
1
7-0
DIS7-DIS0
These bits are set to
“
1
”
every time a DFM status change has occurred since the last
cleared interrupt in transceivers 7-0 respectively.
1. On power up all register bits are set to
“
0
”
.
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