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參數(shù)資料
| 型號： | LXT386BE |
| 英文描述： | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|四|優(yōu)稅PCM-30/E-1 |的CMOS | BGA封裝| 160PIN |塑料 |
| 文件頁數(shù)： | 35/80頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT386BE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
35
2.11
Interfacing with 5V Logic
The LXT384 can interface directly with 5V TTL family devices. The internal input pads are
tolerant to 5V outputs from TTL and CMOS family devices.
2.12
Parallel Host Interface
The LXT384 incorporates a highly flexible 8-bit parallel microprocessor interface. The interface is
generic and is designed to support both non-multiplexed and multiplexed address/data bus systems
for Motorola and Intel bus topologies. Two pins (MUX and MOT/INTL) select four different
operating modes as shown in
Table 5
.
The interface includes an address bus (A4 - A0) and a data bus (D7 - D0) for non-multiplexed
operation and an 8-bit address/data bus for multiplexed operation. WR, RD, R/W, CS, ALE, DS,
INT and RDY/ACK are used as control signals. A significant enhancement is an internal wait-state
generator that controls an Intel and Motorola compatible handshake output signal (RDY/ACK). In
Motorola mode, ACK Low signals valid information is on the data bus. During a write cycle a Low
signal acknowledges the acceptance of the write data.
In Intel mode, RDY High signals to the controlling processor that the bus cycle can be completed.
While Low the microprocessor must insert wait states. This allows the LXT384 to interface with
wait-state capable microcontrollers, independent of the processor bus speed. To activate this
function a reference clock is required on the MCLK pin.
There is one exception to write cycle timing for Intel non-multiplexed mode: Register 0Ah, the
reset register. Because of timing issues, the RDY line remains high after the first part of the cycle is
done, not signalling write cycle completion with another transition low. Add 2 microseconds of
H
Clocked
H
Data Recovery
Pulse Shaping ON
Analog Loopback
H
L
Open
Data Recovery
Power down
No Loopback
H
L
L
Data Recovery
Pulse Shaping OFF
Remote Loopback
H
H
Open
Data Recovery
Pulse Shaping OFF
No Loopback
H
H
L
Data Recovery
Pulse Shaping OFF
Remote Loopback
H
H
H
Data Recovery
Pulse Shaping OFF
Analog Loopback
Table 4. Operation Mode Summary (Continued)
MCLK
TCLK
LOOP
1
Receive Mode
Transmit Mode
Loopback
1. Hardware mode only.
Table 5. Microprocessor Interface Selection
Pin
Operating Mode
MUX
MOT/INTL
Low
Low
Motorola, Non-Multiplexed
Low
High
Intel, Non-Multiplexed
High
Low
Motorola, Multiplexed
High
High
Intel, Multiplexed
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