參數資料
型號： LXT386BE
英文描述： PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC
中文描述： 的PCM收發(fā)器|四|優(yōu)稅PCM-30/E-1 |的CMOS | BGA封裝| 160PIN |塑料
文件頁數： 25/80頁
文件大?。?/td> 1112K
代理商： LXT386BE
Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
25
The AIS condition is cleared when, within two consecutive 512 bit periods, 3 or more zeros
are detected for each 512 bit period.
2.2.2.2
T1 Mode
ANSI T1.231 detection is employed.
The AIS condition is declared when less than 9 zeros are detected in any string of 8192 bits. This
corresponds to a 99.9% ones density over a period of 5.3ms.
The AIS condition is cleared when the received signal contains 9 or more zeros in any string of
8192 bits.
2.2.3
Receive Alarm Indication Signal (RAIS)
The receiver will generate all ones to RPOS and RNEG outputs upon LOS, when bit 6, RAISEN,
for Receive Alarm Indication Signal Enable, is set in the Global Control Register, GCR. This can
affect the AIS status by setting to one if the signal at RTIP and RRING is all zeroes, or be clearing
to zero if the signal at RTIP and RRING is all ones. Because of this, mask the AIS interrupt enable
bits before setting or resetting RAISEN. This will prevent inadvertent interrupts during
programming.
2.2.4
In Service Code Violation Monitoring
In unipolar I/O mode with HDB3/B8ZS decoding, the LXT384 reports bipolar violations on
RNEG/BPV for one RCLK period for every HDB3/B8ZS code violation that is not part of the zero
code substitution rules. In AMI mode, all bipolar violations (two consecutive pulses with the same
polarity) are reported at the BPV output.
2.3
Transmitter
The eight low power transmitters of the LXT384 are identical. Transmit data is clocked serially
into the device at TPOS/TNEG in the bipolar mode or at TDATA in the unipolar mode. The
transmit clock (TCLK) supplies the input synchronization. Unipolar I/O and HDB3/B8ZS/AMI
encoding/decoding is selected by pulling TNEG High for more than 16 consecutive TCLK clock
cycles. The transmitter samples TPOS/TNEG or TDATA inputs on the falling edge of TCLK. Refer
to the Test Specifications Section for MCLK and TCLK timing characteristics. If TCLK is not
supplied, the transmitter remains powered down and the TTIP/TRING outputs are held in a High Z
state. In addition, fast output tristatability is also available through the OE pin (all ports) and/or the
port
’
s OEx bit in the Output Enable Register (OER).
Zero suppression is available only in Unipolar Mode. The two zero-suppression types are B8ZS,
used in T1 environments, and HDB3, used in E1 environments. The scheme selected depends on
whether the device is set for T1 or E1 operation (determined by LEN2-0 pulse shaping settings).
The LXT384 also supports AMI line coding/decoding as shown in
Figure 5
. In Hardware mode,
AMI coding/decoding is selected by the CODEN pin. In host mode, AMI coding/decoding is
selected by bit 4 in the GCR (Global Control Register).
相關PDF資料
PDF描述
LXT386LE PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC
LXT388LE PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC
LXT400JE Hermetically Sealed, 3.3V, High Speed, High CMR, Logic Gate Optocoupler
LXT6155LE Telecomm/Datacomm
LXT6251A ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC
相關代理商/技術參數
參數描述
LXT386LE 制造商:LEVEL1 功能描述:
LXT388LE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC
LXT400 制造商:LVL1 制造商全稱:LVL1 功能描述:All Rate Extended Range Switched 56/DDS Transceiver
LXT400JE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transceiver Circuit For Telecommunications
LXT441 制造商:LVL1 制造商全稱:LVL1 功能描述:Switched 56/DDS Integrated DSU/CSU
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯系方式

*
*
*