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參數(shù)資料
| 型號： | LU3X34FTR |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器（四通道1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 33/52頁 |
| 文件大小： | 678K |
| 代理商： | LU3X34FTR |
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Lucent Technologies Inc.
33
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
12
10 Mbits/s Full Duplex
1—Capable of 10 Mbits/s full-duplex
mode
0—Not capable of 10 Mbits/s full-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FTR supports 10Base-T
full-duplex mode.
1—Capable of 10 Mbits/s half-duplex
mode
0—Not capable of 10 Mbits/s half-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FTR supports 10Base-T
half-duplex mode.
1—Capable of 100Base-T2
0—Not capable of 100Base-T2
This bit is hardwired to 0, indicating that
the LU3X34FTR does not support
100Base-T2.
Ignore when read.
RO
1h
11
10 Mbits/s Half Duplex
RO
1h
10
100Base-T2
RO
0h
9:7
6
Reserved
RO
RO
0h
1h
MF Preamble Suppression 1—Accepts management frames with
preamble suppressed
0—Will not accept management frames
with preamble suppressed
This bit is hardwired to 1, indicating that
the LU3X34FTR accepts management
frame without preamble. A minimum of 32
preamble bits are required following
power-on or hardware reset. One idle bit
is required between any two manage-
ment transactions as per IEEE802.3u
specification.
Autonegotiation Complete
1—Autonegotiation process completed
0—Autonegotiation process not com-
pleted
If autonegotiation is enabled, this bit indi-
cates whether the autonegotiation pro-
cess has been completed.
Remote Fault
1—Remote fault detected
0—Remote fault not detected
This bit is latched to 1 if the RF bit in the
autonegotiation link partner ability regis-
ter (bit 13, register address 05h) is set or
the receive channel meets the far-end
fault indication function criteria. It is
unlatched when this register is read.
5
RO
0h
4
RO, LH
0h
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 15. Status Register Bit Definitions (Register 1h)
(continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FT | Quad-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
| LU5X34F | Quad Gigabit Ethernet Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
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