參數(shù)資料
型號(hào)： LU3X34FTR
廠商： Lineage Power
英文描述： Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器)
中文描述： 四3伏10/100以太網(wǎng)收發(fā)器（四通道1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器）
文件頁數(shù)： 14/52頁
文件大?。?/td> 678K
代理商： LU3X34FTR
14
Lucent Technologies Inc.
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
Functional Description
(continued)
Transmit Data Path
The PHY uses the 50 MHz REF_CLK as its reference
so that TXC (at the internal MII) and REF_CLK main-
tain a phase relationship. This helps to avoid elasticity
buffers on the transmit side. On the rising edge of
REF_CLK, 2-bit data is provided on the RMII TXD[1:0]
when TXEN is high. TXD[1:0] will be 00 to indicate idle
when TXEN is deasserted.
TX 10 Mbits/s Mode
The REF_CLK frequency is ten times the data rate in
this mode; therefore, the value on TXD[1:0] will be valid
such that TXD[1:0] may be sampled every tenth cycle,
regardless of the starting cycle within the group.
TX 100 Mbits/s Mode
There will be valid data on TXD[1:0] for each REF_CLK
period when TXEN is asserted.
Receive Data Path
RXCLK (at the internal MII) is derived from the incom-
ing data and, hence, does not maintain a phase rela-
tionship with REF_CLK. Therefore, an elasticity buffer
is required on the receive path. An 8-nibble deep elas-
ticity buffer is required based on the ppm variation of
the clocks. CRS_DV is asserted asynchronously. Pre-
amble is output onto the RMII once the internal signal
RX_DV is asserted (on the rising edge of the
REF_CLK). CRS_DV is deasserted asynchronously
with the fall of RX_DV, but CRS_DV keeps toggling as
long as data is being flushed out of the elasticity buffer.
RX 10 Mbits/s Mode
After the assertion of CRS_DV, the receive data sig-
nals, RXD[1:0], will be 00 until the 10Base-T PHY has
recovered the clock and decoded the receive data.
Since REF_CLK is 10 times the data rate in this mode,
the value on RXD[1:0] will be valid such that it can be
sampled every tenth cycle, regardless of the starting
cycle within the group.
RX 100 Mbits/s Mode
After the assertion of CRS_DV, the receive data sig-
nals, RXD[1:0] will be 00 until the start-of-stream (SSD)
delimiter has been detected.
Collision Detection
The RMII does not have a collision signal, so all colli-
sions are detected internal to the MAC. This is an AND
function of TXEN and CRS derived from CRS_DV.
CRS_DV cannot be directly ANDed with TXEN,
because CRS_DV may toggle at the end of a frame to
provide separation between CRS and RXDV.
Receiver Error
The RX_ER signal is asserted for one or more
REF_CLK periods to indicate that an error was
detected within the current receive frame.
5-7506(F).r2
Figure 5. RMII Receive Timing from Internal MII Signals
REF_CLK
CRS
RX_DV
CRS_DV
RMII_RXD[1:0]
00
01
01
00
CRS
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