參數(shù)資料
型號(hào)： LU3X34FTR
廠商： Lineage Power
英文描述： Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器)
中文描述： 四3伏10/100以太網(wǎng)收發(fā)器（四通道1000萬(wàn)位/秒和100海里位/秒以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 678K
代理商： LU3X34FTR
Lucent Technologies Inc.
17
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description
(continued)
Media Independent Interface (MII)—Internal
The LU3X34FTR implements IEEE802.3u Clause 22
compliant MII interface which connects to the MII-RMII
module. This module converts the 4-bit MII receive
data to 2-bit RMII receive data. Similarly, it converts the
2-bit RMII transmit data (received from the MAC) to
4-bit MII transmit data. The following describes the
internal MII functions.
Transmit Data Interface
Each internal MII transmit data interface comprises
seven signals: TXD[3:0] are the nibble size data path,
TXEN signals the presence of data on TXD, TXER indi-
cates substitution of data with the HALT symbol, and
TXCLK carries the transmit clock that synchronizes all
the transmit signals. TXCLK is usually supplied by the
on-chip clock synthesizer.
Receive Data Interface
Each internal MII receive data interface also comprises
seven signals: RXD[3:0] are the nibble size data path,
RXDV signals the presence of data on RXD, RXER
indicates the validity of data, and RXCLK carries the
receive clock. Depending upon the operation mode,
RXCLK signal is generated by the clock recovery mod-
ule of either the 100Base-X or 10Base-T receiver.
Status Interface
Two internal MII status signals, COL and CRS, are gen-
erated in each of the four channels to indicate collision
status and carrier sense status. COL is asserted asyn-
chronously whenever the respective channel of
LU3X34FTR is transmitting and receiving at the same
time in a half-duplex operation mode. CRS is asserted
asynchronously whenever there is activity on either the
transmitter or the receiver. In repeater or full-duplex
mode, CRS is asserted only when there is activity on
the receiver.
Operation Modes
Each channel of the LU3X34FTR supports two opera-
tion modes and an isolate mode as described below.
100 Mbits/s Mode
. For 100 Mbits/s operation, the
internal MII operates in nibble mode with a clock rate of
25 MHz. In normal operation, the internal MII data at
RXD[3:0] and TXD[3:0] are 4 bits wide.
10 Mbits/s Mode
. For 10 Mbits/s nibble mode opera-
tion, the TXCLK and RXCLK operate at 2.5 MHz. The
data paths are 4 bits wide using TXD[3:0] and
RXD[3:0] signal lines.
MII Isolate Mode
. The LU3X34FTR implements an MII
isolate mode that is controlled by bit 10 of each one of
the four control registers (register 0h). At reset,
LU3X34FTR will initialize this bit to the logic level tran-
sition of the ISOLATE pin. Setting the bit to a 1 will also
put the port in MII isolate mode.
When in isolate mode, the specified port on the
LU3X34FTR does not respond to packet data present
at TXD[3:0], TXEN, and TXER inputs and presents a
high impedance on the TXCLK, RXCLK, RXDV, RXER,
RXD[3:0], COL, and CRS outputs. The LU3X34FTR
will continue to respond to all management transac-
tions while the PHY is in isolate mode.
Serial Management Interface (SMI)
The serial management interface is used to obtain sta-
tus and to configure the PHY. This mechanism corre-
sponds to the MII specifications for 100Base-X (Clause
22), and supports registers 0 through 6. Additional ven-
dor-specific registers are implemented within the range
of 16 to 31. All the registers are described in the MII
Registers section.
Management Register Access
The SMI consists of two pins, management data clock
(MDC) and management data input/output (MDIO).
The LU3X34FTR is designed to support an MDC fre-
quency specified in the IEEEspecification of up to
2.5 MHz. The MDIO line is bidirectional and may be
shared by up to 32 devices.
The MDIO pin requires a 1.5 k
pull-up resistor which,
during idle and turnaround periods, will pull MDIO to a
logic one state. Each MII management data frame is
64 bits long. The first 32 bits are preamble consisting of
32 contiguous logic one bits on MDIO and 32 corre-
sponding cycles on MDC. Following preamble is the
start-of-frame field indicated by a <01> pattern. The
next field signals the operation code (OP): <10> indi-
cates read from MII management register operation,
and <01> indicates write to MII management register
operation. The next two fields are PHY device address
and MII management register address. Both of them
are 5 bits wide, and the most significant bit is trans-
ferred first.
During read operation, a 2-bit turnaround (TA) time
spacing between the register address field and data
field is provided for the MDIO to avoid contention. Fol-
lowing the turnaround time, a 16-bit data stream is read
from or written into the MII management registers of
the LU3X34FTR.
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