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參數(shù)資料
| 型號： | LU3X34FTR |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器（四通道1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 29/52頁 |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR |
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Lucent Technologies Inc.
29
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description
(continued)
Autonegotiation and Speed Configuration
The four sets of five pins listed in Table 13 configure the speed capability of each channel of LU3X34FTR. The
logic state of these pins, at powerup or reset, is latched into the advertisement register (register address 04h) for
autonegotiation purposes. These pins are also used for evaluating the default value in the base mode control reg-
ister (register 00h) according to Table 12.
Table 12. Autonegotiation
LED Configuration
The LU3X34FTR provides four LED output pins for each of its four ports. In addition to the default functions associ-
ated with their pin names, there are several registers that allow users to customize LED operations.
Register 11h (programmable LED register) at PHY address 2 implements even more flexible LED configurations.
Register 11h at PHY address 4 controls all even-numbered ports, and register 11h at address 5 controls all odd-
numbered ports. Via the programmable LED register, each of the LEDs may be configured to operate in one of the
following modes: link, speed, duplex, receive, transmit, solid when link is up and blinks during activity, remote fault,
and collision. Bits [0:3] in these registers allow the user to invert the on/off logic for each of these four programma-
ble LEDs individually.
Note that all LED circuits are switched under the control of the programmable LED register whenever the content of
register 11h differs from its default value.
Register 17h implements more LED configuration functions. With these registers, unused LED can be individually
turned off to reduce power consumption.
Fiber Mode Select
A logic one level on pins FOSEL[0:3] sets each channel in fiber mode individually. These pins are latched during
reset operation.
MII Registers
The LU3X34FTR has four independent PHYs in it. Each PHY has its own identical set of registers as tabulated
below. The PHY address differentiates which PHY to be read or written into. The following tables of registers are
applicable to each register.
Configuration Pins at Reset
Registers Initial Value
ANEN
FD100
(bit 4.8)
1
0
0
0
0
X
HD100
(bit 4.7)
X
1
1
0
0
X
FD10
(bit 4.6)
X
1
0
1
0
X
HD10
(bit 4.5)
X
X
X
X
1
X
AUTONEG
reg 0.12
0
0
0
0
0
1
SPEED
reg 0.13
1
1
1
0
0
0
DUPLEX
reg 0.8
1
1
0
1
0
0
0
0
0
0
0
1
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相關(guān)代理商/技術(shù)參數(shù) |
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| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
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| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
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