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參數(shù)資料
| 型號(hào)： | LU3X34FTR |
| 廠商： | Lineage Power |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器（四通道1000萬(wàn)位/秒和100海里位/秒以太網(wǎng)收發(fā)器） |
| 文件頁(yè)數(shù)： | 10/52頁(yè) |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR |
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LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
10
Lucent Technologies Inc.
* Smaller font indicates that the pin has multiple functions.
Table 6. LED/Configuration Pins
58
MDC
I
I
Management Clock.
Max clock rate = 2.5 MHz.
Reserved.
Tie to ground.
53, 55, 73, 75,
97, 99, 111
57, 69, 77, 86,
90, 95, 102,
109
RESERVED
RESERVED
0
Reserved.
Let this pin float.
Pin No.
80, 81, 82, 85
Pin Name
FD10_[0:3]
I/O
I
Pin Description
Full-Duplex 10 Mbits/s
. These pins are latched at
reset to configure the ports to 10 Mbits/s full-duplex
mode if autonegotiation is disabled. These pins will
set bit [6] in register 4h, the autonegotiation ability
register.
Full-Duplex 100 Mbits/s.
In switch mode, these pins
are latched at reset to configure the ports to
100 Mbits/s full-duplex mode if autonegotiation is
disabled. These pins will set bit [8] in register 4h, the
autonegotiation ability register. These inputs have
internal 40 k
pull-up resistors.
100, 93, 79,
68
FD100_[0:3]/
COL_[0:3]
I
↑
Collision Status Output
. It is asserted during half-
duplex mode when transmit and receive activities
are active simultaneously.
Speed LED Output
. In twisted-pair mode, these
LED outputs indicate 100 Mbits/s line speed for
ports 0—3.
115, 121, 43,
49
LEDSP100_ [0:3]/
ANEN_[0:3]/
SD+[0:3]
I/O
↑
Autonegotiation Enable
. If the FOSEL pin detects
logic low during reset, these are input pins to config-
ure ports 0—3 to enable autonegotiation and sets bit
12 in register 0h.
Signal Detect +
. In fiber mode, these pins are signal
detect + inputs.
These pins have an internal 40 k
pull-up resistor.
Pin No.
Pin Name*
I/O
Pin Description
Pin Descriptions
(continued)
Table 5. MII Interface (SMII Mode)
(continued)
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PDF描述 |
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| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
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| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FT | Quad-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X34FTR-HS128-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
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