參數(shù)資料
型號(hào)： LU3X34FTR
廠商： Lineage Power
英文描述： Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器)
中文描述： 四3伏10/100以太網(wǎng)收發(fā)器（四通道1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 18/52頁(yè)
文件大?。?/td> 678K
代理商： LU3X34FTR
18
Lucent Technologies Inc.
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
Functional Description
(continued)
The LU3X34FTR supports a preamble suppression
mode as indicated by a 1 in bit 6 of the basic mode sta-
tus register (BMSR, address 01h). If the station man-
agement entity (i.e., MAC or other management
controller) determines that all PHYs in the system sup-
port preamble suppression by reading a 1 in this bit,
then the station management entity need not generate
preamble for each management transaction. The
LU3X34FTR requires a single initialization sequence of
32 bits of preamble following powerup/hardware reset.
This requirement is generally met by the mandatory
pull-up resistor on MDIO or the management access
made to determine whether preamble suppression is
supported. While the LU3X34FTR will respond to man-
agement accesses without preamble, a minimum of
one idle bit between management transactions is
required as specified in IEEE802.3u.
The PHY device address is stored in bits [4:0] of the
PHY address register (register address 19h). During
powerup or hardware reset, the upper 3 bits of this field
are initialized by the three I/O pins designated as
PHY[4:2] and can be subsequently changed by writing
into this register address (19h). The lower 2 bits are ini-
tialized to 00, and represent the PHY address for port
1. All subsequent ports have their PHY address incre-
ment from this base address (i.e., PHY address for port
1 = 10h, PHY address for port 2 = 11h, PHY address
for port 3 = 12h, PHY address for port 4 = 13h).
MDIO Interrupt
The LU3X34FTR implements interrupt capability that
can be used to notify the management station of cer-
tain events. Interrupt requested by any of the four PHYs
is combined in this pin. It generates an active-low inter-
rupt pulse of 80 ns wide on the INTZ output pin when-
ever one of the interrupt status registers (register
address 1Eh) becomes set while its corresponding
interrupt mask register (register address 1Dh) is un-
masked. Reading the interrupt status register (register
1Eh) shows the source of the interrupt and clears the
interrupt output signal.
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