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參數(shù)資料
| 型號(hào)： | LU3X34FTR-HS128-DB |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁數(shù)： | 9/52頁 |
| 文件大小： | 678K |
| 代理商： | LU3X34FTR-HS128-DB |
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Lucent Technologies Inc.
9
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
* Smaller font indicates that the pin has multiple functions.
Table 5. MII Interface (SMII Mode)
90
78
RMII_RXER_1
CRS_DV_2/
PHYAD[3]
O
Receiver Error Output for Port 1
.
CRS_DV Output for Port 2
. During reset, this is an
input pin for PHY_address[3] configuration. This pin
has an internal 40 k
pull-down resistor that sets the
PHY_AD[3] to a 0 without an external component.
After reset, CRS_DV output for port 2 and is
asserted only during receive activity.
Transmit Data for Port 2
.
Receive Data for Port 2
.
Receiver Error for Port 2
.
CRS_DV Output for Port 3
. During reset, this is an
input pin for PHY_address[4] configuration. This pin
has an internal 40 k
pull-down resistor that sets the
PHY_AD[4] to a 0 without an external component.
After reset, CRS_DV output for port 3 and is
asserted only during receive activity.
Transmit Data for Port 3
.
Receive Data for Port 3
.
Receive Error Output for Port 3
.
Management Data for Serial Register Access
.
Management Clock.
Max clock rate = 2.5 MHz.
Reserved
. Leave this pin float.
I/O
↓
74, 75
76, 77
86
67
RMII_TXD_2[0:1]
RMII_RXD_2[0:1]
RMII_RXER_2
CRS_DV_3/
PHYAD[4]
I/O
O
O
I/O
↓
54, 55
56, 57
69
59
58
65, 87, 70
RMII_TXD_3[0:1]
RMII_RXD_3[0:1]
RMII_RXER_3
MDIO
MDC
RESERVED
I
I/O
O
I/O
I
O
Pin No.
113
112
110
101
Pin Name*
SMII_SYNC
SMII_TXD_0
SMII_RXD_0
SMII_EN
I/O
I
I
I/O
I/O
↓
Pin Description
SMII Sync Input.
Transmit Data for Port 0.
Receive Data for Port 0.
SMII_EN.
This pin must be pulled high at powerup or
reset to enable SMII mode. This input has an inter-
nal 40 k
pull-down resistor.
Transmit Data for Port 1.
Receive Data for Port 1.
Configure PHY Address
. These pins configure
PHY_address 4 through 2 at powerup or reset. Each
of these pins has an internal 40 k
pull-down resis-
tor that sets the corresponding PHY_AD to 0, with-
out an external component.
Transmit Data for Port 3.
Receive Data for Port 3.
Transmit Data for Port 2.
Receive Data for Port 2.
Management Data for Serial Register Access
. An
external resistive pull-up is needed on this pin.
98
96
SMII_TXD_1
SMII_RXD_1
PHYAD[4:2]
I/O
O
I/O
67, 78, 94
54
56
74
76
59
SMII_TXD_3
SMII_RXD_3
SMII_TXD_2
SMII_RXD_2
MDIO
I
I/O
I/O
O
I/O
Pin No.
Pin Name*
I/O
Pin Description
Pin Descriptions
(continued)
Table 4. MII Interface (RMII Mode)
(continued)
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