- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369872 > LU3X34FTR-HS128-DB Quad 3 V 10/100 Ethernet Transceiver TX/FX PDF資料下載
參數(shù)資料
| 型號： | LU3X34FTR-HS128-DB |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR-HS128-DB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Preliminary Data Sheet
July 2000
32
Lucent Technologies Inc.
Note: While maintaining a good link, modifying any bit in the control register (register 0) will cause the link to drop.
Table 15. Status Register Bit Definitions (Register 1h)
9
Restart Autonegotiation
1—Restart autonegotiation process
0—Normal operation
Setting this bit while autonegotiation is
enabled forces a new autonegotiation pro-
cess to start. This bit is self-clearing and
returns to 0 after the autonegotiation pro-
cess has commenced.
1—Full-duplex mode
0—Half-duplex mode
If autonegotiation is disabled, this bit
determines the duplex mode for the link.
At powerup or reset, this bit is set to 0 if
the SW_RPTRZ input is low. This bit is set
to 1, if ANEN pin detects a logic 0 and
either FD100 or FD10 pin detects a logic
1.
1—Enable COL signal test
0—Disable COL signal test
When set, this bit will cause the COL sig-
nal of MII interface to be asserted in
response to the assertion of TXEN.
Not used.
R/W, SC
0h
8
Duplex Mode
R/W
Pin
7
Collision Test (only
applicable while in PHY
loopback mode)
R/W
0h
6:0
Reserved
RO
0h
Bit(s)
15
Name
Description
R/W
RO
Default
0h
100Base-T4
1—Capable of 100Base-T4
0—Not capable of 100Base-T4
This bit is hardwired to 0, indicating that
the LU3X34FTR does not support
100Base-T4.
1—Capable of 100Base-X full-duplex
mode
0—Not capable of 100Base-X full-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FTR supports 100Base-X
full-duplex mode.
1—Capable of 100Base-X half-duplex
mode
0—Not capable of 100Base-X half-duplex
mode
This bit is hardwired to 1, indicating that
the LU3X34FTR supports 100Base-X
half-duplex mode.
14
100Base-X Full Duplex
RO
1h
13
100Base-X Half Duplex
RO
1h
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 14. Control Register (Register 0h)
(continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X34FTR | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FT | Quad-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX(應用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208-DB | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208-DB |
發(fā)布緊急采購，3分鐘左右您將得到回復。