參數(shù)資料
型號: LU3X34FTR-HS128-DB
英文描述: Quad 3 V 10/100 Ethernet Transceiver TX/FX
中文描述: 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯
文件頁數(shù): 39/52頁
文件大?。?/td> 678K
代理商: LU3X34FTR-HS128-DB
Lucent Technologies Inc.
39
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Table 25. Config 100 Register (Register 18h)
10
MF Preamble Suppression
Enable
1—MDIO preamble suppression enabled
0—MDIO preamble suppression disabled
LU3X34FTR can accept management
frames without preamble as described in
bit 6 of register 1h. This bit allows the user
to enable or disable the preamble sup-
pression function.
1—Part is in 100 Mbit mode
0—Part is in 10 Mbit mode
This value is not defined during the auto-
negotiation period.
1—Part is in full-duplex mode
0—Part is in half-duplex mode
This value is not defined during the auto-
negotiation period.
Reserved.
Reserved.
1—3-state ACTLED output
0—Normal operation
1—3-state LEDLNK output
0—Normal operation
Reserved.
1—3-state LEDFD output
0—Normal operation
1—3-state LEDSP output
0—Normal operation
R/W
1h
9
Speed Status
RO
0h
8
Duplex Status
RO
0h
7
6
5
Reserved
Reserved
ACTLED Off
R/W
R/W
R/W
1h
1h
0
4
LEDLNK Off
R/W
0
3
2
Reserved
LEDFD Off
R/W
R/W
1h
0
1
LEDSP Off
R/W
0
0
LED Pulse Stretching Disable 1—LED pulse stretching disabled
0—LED pulse stretching enabled
When set to 1 all LED outputs are
stretched 48 ms—72 ms.
R/W
0
Bit(s)
15
Name
BPSCR
Description
R/W
R/W
Default
FOSEL
1—Disable scrambler/descrambler
0—Enable scrambler/descrambler
Reserved.
Reserved.
Reserved.
14
13
12
Reserved
Reserved
Reserved
RO
RO
RO
0h
0h
0h
Bit(s)
Name
Description
R/W
Default
MII Registers
(continued)
Table 24. PHY Control/Status Register (Register 17h)
(continued)
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