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參數(shù)資料
| 型號： | LU3X34FTR-HS128-DB |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁數(shù)： | 13/52頁 |
| 文件大小： | 678K |
| 代理商： | LU3X34FTR-HS128-DB |
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Lucent Technologies Inc.
13
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description
The LU3X34FTR integrates four 100Base-X physical
sublayers (PHY), 100Base-TX physical medium depen-
dent (PMD) transceivers, and four complete 10Base-T
modules into a single chip for both 10 Mbits/s and
100 Mbits/s Ethernet operation. It also supports
100Base-FX operation through external fiber-optic
transceivers. This device provides a reduced media
independent interface (RMII) or serial media indepen-
dent interface (SMII) to communicate between the
physical signaling and the medium access control
(MAC) layers for both 100Base-X and 10Base-T opera-
tions. The device is capable of operating in either full-
duplex mode or half-duplex mode in either 10 Mbits/s or
100 Mbits/s operation. Operational modes can be
selected by hardware configuration pins or software
settings of management registers, or can be deter-
mined by the on-chip autonegotiation logic.
The 10Base-T section of the device consists of the
10 Mbits/s transceiver module with filters and a
Manchester ENDEC module.
The 100Base-X section of the device implements the
following functional blocks:
I
100Base-X physical coding sublayer (PCS).
I
100Base-X physical medium attachment (PMA).
I
Twisted-pair transceiver (PMD).
The 100Base-X and 10Base-T sections share the fol-
lowing functional blocks:
I
Clock synthesizer module (CSM).
I
MII registers.
I
IEEE 802.3u autonegotiation.
Additionally, there is an interface module that converts
the internal MII signals of the PHY to RMII signal pins.
Each of these functional blocks is described below.
Reduced Media Independent Interface (RMII)
This interface reduces the interconnect circuits
between a MAC and PHY. In switch applications, this
protocol helps to reduce the pin count on the switch
ASIC significantly. A regular 16-pin MII reduces to a
7-pin (8-pin with an optional RXER pin) RMII. The
interconnect circuits are the following:
1. REF_CLK: A 50 MHz clock.
2. TX_EN.
3. TXD[1:0].
4. RXD[1:0].
5. CRS_DV.
6. RXER: Mandatory for the PHY, but optional for the
switch.
5-7505(F).r1
Figure 4. Functional Description
TXEN
TXD[3:0]
TXER
TXCLK
COL
CRS
RXDV
RXD[3:0]
RXER
RXCLK
TXEN
TXD[3:0]
TXER
TXCLK
COL
CRS
RXDV
RXD[3:0]
RXER
RXCLK
MII MAC I/F TO RMII MAC I/F
MAC
RMII
PHY
RMII PHY I/F TO MII PHY I/F
TXEN
TXD[1:0]
CRS_DV
RXD[1:0]
RXER
REFCLK
50 MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X34FTR | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FT | Quad-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208-DB | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208-DB |
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