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參數(shù)資料
| 型號： | LU3X34FTR-HS128-DB |
| 英文描述： | Quad 3 V 10/100 Ethernet Transceiver TX/FX |
| 中文描述： | 四3伏10/100以太網(wǎng)收發(fā)器德克薩斯州/外匯 |
| 文件頁數(shù)： | 23/52頁 |
| 文件大?。?/td> | 678K |
| 代理商： | LU3X34FTR-HS128-DB |
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Lucent Technologies Inc.
23
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Functional Description
(continued)
In order to maintain synchronization, the descrambler
continuously monitors the validity of the unscrambled
data that it generates. To ensure this, a link state moni-
tor and a hold timer are used to constantly monitor the
synchronization status. Upon synchronization of the
descrambler, the hold timer starts a 722
μ
s countdown.
Upon detection of sufficient idle symbols within the
722
μ
s period, the hold timer will reset and begin a new
countdown. This monitoring operation will continue
indefinitely given a properly operating network connec-
tion with good signal integrity. If the link state monitor
does not recognize sufficient unscrambled idle symbols
within the 722
μ
s period, the descrambler will be forced
out of the current state of synchronization and reset in
order to reacquire synchronization. Register 18h, bit 3,
can be used to extend the timer to 2 ms.
Symbol Alignment
The symbol alignment circuit in the LU3X34FTR deter-
mines code word alignment by recognizing the /J/K
delimiter pair. This circuit operates on unaligned data
from the descrambler. Once the /J/K symbol pair
(11000 10001) is detected, subsequent data is aligned
on a fixed boundary.
Symbol Decoding
The symbol decoder functions as a look-up table that
translates incoming 5B symbols into 4B nibbles. The
symbol decoder first detects the /J/K symbol pair pre-
ceded by idle symbols and replaces the symbol with
MAC preamble. All subsequent 5B symbols are con-
verted to the corresponding 4B nibbles for the duration
of the entire packet. This conversion ceases upon the
detection of the /T/R symbol pair denoting the end-of-
stream delimiter (ESD). The translated data is pre-
sented on the RXD[3:0] signal lines with RXD[0] repre-
sents the least significant bit of the translated nibble.
Valid Data Signal
The valid data signal (RXDV) indicates that recovered
and decoded nibbles are being presented on the
RXD[3:0] outputs synchronous to RXCLK. RXDV is
asserted when the first nibble of translated /J/K is
ready for transfer over the internal MII. It remains active
until either the /T/R delimiter is recognized, link test
indicates failure, or no signal is detected. On any of
these conditions, RXDV is deasserted.
Receiver Errors
The RXER signal is used to communicate receiver
error conditions. While the receiver is in a state of hold-
ing RXDV asserted, the RXER will be asserted for each
code word that does not map to a valid code-group.
100Base-X Link Monitor
The 100Base-X link monitor function allows the
receiver to ensure that reliable data is being received.
Without reliable data reception, the link monitor will halt
both transmit and receive operations until such time
that a valid link is detected.
The LU3X34FTR performs the link integrity test as out-
lined in IEEE100Base-X (Clause 24) link monitor state
diagram. The link status is multiplexed with 10 Mbits/s
link status to form the reportable link status bit in serial
management register 1 and driven to the LNKLED
pins.
When persistent signal energy is detected on the net-
work, the logic moves into a link-ready state after
approximately 500
μ
s and waits for an enable from the
autonegotiation module. When received, the link-up
state is entered, and the transmit and receive logic
blocks become active. Should autonegotiation be dis-
abled, the link integrity logic moves immediately to the
link-up state after entering the link-ready state.
Carrier Sense
Carrier sense (CRS) for 100 Mbits/s operation is
asserted upon the detection of two noncontiguous
zeros occurring within any 10-bit boundary of the
receive data stream.
The carrier sense function is independent of symbol
alignment. In switch mode, CRS is asserted during
either packet transmission or reception. For repeater
mode, CRS is asserted only during packet reception.
When the idle symbol pair is detected in the receive
data stream, CRS is deasserted. In repeater mode,
CRS is only asserted due to receive activity. CRS is
intended to encapsulate RXDV.
Bad SSD Detection
A bad start-of-stream delimiter (bad SSD) is an error
condition that occurs in the 100Base-X receiver if car-
rier is detected (CRS asserted) and a valid /J/K set of
code-groups (SSD) is not received.
If this condition is detected, then the LU3X34FTR will
assert RXER and present RXD[3:0] = 1110 to the inter-
nal MII for the cycles that correspond to received 5B
code-groups until at least two idle code-groups are
detected. In addition, the false carrier counter (address
13h) will be incremented by one. Once at least two idle
code-groups are detected, RXER and CRS become
deasserted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LU3X34FTR | Quad 3 V 10/100 Ethernet Transceiver(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器) |
| LU3X54FT | QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTL-HS208-DB | QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FT | Quad-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX(應(yīng)用于10基數(shù)-T和100基數(shù)-TX/FX的四快速以太網(wǎng)收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU3X54FT | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX |
| LU3X54FTL | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208 | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208 |
| LU3X54FTL-HS208-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:QUAD-FET for 10Base-T/100Base-TX/FX |
| LU3X54FTLHS208-DB | 制造商:Alcatel-Lucent 功能描述:3X54FTLHS208-DB |
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