參數(shù)資料
型號(hào)： LF3370
廠商： Logic Devices Incorporated
英文描述： High-Definition Video Format Converter(高清晰度視頻格式轉(zhuǎn)換器)
中文描述： 高清晰度視頻格式轉(zhuǎn)換器（高清晰度視頻格式轉(zhuǎn)換器）
文件頁(yè)數(shù)： 15/22頁(yè)
文件大?。?/td> 256K
代理商： LF3370
DEVICES INCORPORATED
Video Imaging Products
15
LF3370
High-Definition Video Format Converter
08/21/2000–LDS.3370-E
Table 33 shows an example of loading a
Configuration Register. In this example,
Configuration Register 0 (0200H) is
loaded with 00AEH. This will setup the
Input Section to handle Luma on input
port A
12-0
and interleaved Chroma on the
input port B
12-0
. The Output Section is
setup to output RGB on the output ports
W
12-0
, X
12-0
, Y
12-0
. The ‘functional
arrangement’ is setup in such a way that
the Half-Band Filter section is placed
before the Matrix Multiplier section. The
Half-Band Filters are setup for 1:2
interpolation and ‘normal order of
operations’ is selected.
BYPASS OPTIONS
Core Bypass
At all times during the normal operation
of the LF3370, video data on channels A,
B, C, and D are simultaneously being fed
from the output of the Input
Demultiplexer into the programmable
Core Bypass Delay (see Figure 15). This
allows users to switch between processed
video and unprocessed (bypassed) data
on-the-fly.
There is a separate Core Bypass Delay for
each channel. Each Core Bypass Delay
can be programmed for a length of 2 up to
129 CLK cycles for delay matching
between the bypass path and the core as
well as other operations. The Core Bypass
Delay bypasses the Input Bias, Input LUT,
Half-Band Filter, Matrix Multiplier/Key
Scaler Section, and Output Bias and feeds
the Output Multiplexer. Loading
Configuration Register 2 programs the
length of all four Core Bypass Delays (see
Table 7).
A LOW state detected on DATAPASS on
a rising edge of clock will output by-
passed data to the output port on the
following rising edge of CLK (see Figure
X). In addition, any of the four bypassed
channels can be passed to the ‘W’ output
channel during a ‘bypass’ event. For this
operation, use bits 7 and 8 of Configura-
tion Register 1 (see Table 6).
Half-Band Filter Bypass
At all times, while data is being fed into
the Half-Band Filter section, channels A,
B, C, and Key are fed into programmable
length delays. When the Half-Band
Filter(s) are set to filter bypass mode, that
particular channel passes through a
programmable delay and is not filtered.
Since there are only two Half-Band Filters
in this section found on channels B and C,
channels A and Key are passed through
their respective programmable delays.
Please note, when using a single channel
video input or video output (interleaved
4:2:2), the Core Bypass Delay must be
programmed to double the length
[(desired length x 2) – 2)] to properly
align data due to the core running at
half the CLK rate.
First Operation Select
‘First Operation Select’ is a bypassing
option where you select to use the first
functional block (Half-Band Filter or
Matrix Multiplier/Key Scaler) in any given
arrangement. If the device was arranged
in such a way that the Half-Band Filter
section fed the Matrix Multiplier/Key
Scaler section and ‘First Operation Select’
was enabled, the Half-Band Filter section
will be used and the Matrix Multiplier/
Key Scaler section will be bypassed.
BITS
FUNCTION
DESCRIPTION
6-0
Core Bypass Delay Length
Length of Core Bypass Delay Minus 2
12-7
Reserved
Must be Set to Zero
T
ABLE
7.
C
ONFIGURATION
R
EGISTER
2 – A
DDRESS
202H
BITS
FUNCTION
DESCRIPTION
6-0
Channel ‘A’ Filter Section
Bypass Delay Length
Length of Filter Bypass Delay Minus 2
12-7
Reserved
Must be Set to Zero
T
ABLE
8.
C
ONFIGURATION
R
EGISTER
3 – A
DDRESS
203H
BITS
FUNCTION
DESCRIPTION
6-0
Channel ‘B’ Filter Section
Bypass Delay Length
Length of Filter Bypass Delay Minus 2
12-7
Reserved
Must be Set to Zero
T
ABLE
9.
C
ONFIGURATION
R
EGISTER
4 – A
DDRESS
204H
BITS
FUNCTION
DESCRIPTION
6-0
Key Channel Filter Section
Bypass Delay Length
Length of Filter Bypass Delay Minus 2
12-7
Reserved
Must be Set to Zero
T
ABLE
11.
C
ONFIGURATION
R
EGISTER
6 – A
DDRESS
206H
BITS
FUNCTION
DESCRIPTION
6-0
Channel ‘C’ Filter Section
Bypass Delay Length
Length of Filter Bypass Delay Minus 2
12-7
Reserved
Must be Set to Zero
T
ABLE
10.
C
ONFIGURATION
R
EGISTER
5 – A
DDRESS
205H
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LF3370QC12 制造商:LOGIC 制造商全稱:LOGIC 功能描述:High-Definition Video Format Converter
LF33AB 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Very low drop voltage regulators with inhibit
LF33ABDT 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
LF33ABDT-TR 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
LF33ABP 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
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