參數(shù)資料
型號(hào)： LF3370
廠商： Logic Devices Incorporated
英文描述： High-Definition Video Format Converter(高清晰度視頻格式轉(zhuǎn)換器)
中文描述： 高清晰度視頻格式轉(zhuǎn)換器（高清晰度視頻格式轉(zhuǎn)換器）
文件頁數(shù)： 14/22頁
文件大?。?/td> 256K
代理商： LF3370
DEVICES INCORPORATED
LF3370
High-Definition Video Format Converter
14
08/21/2000–LDS.3370-E
Video Imaging Products
Interface. A RSL register is not written
to until all four data words are loaded.
After the last data value is loaded, the
interface will expect a new address value
on the next clock cycle. After the next
address value is loaded, data loading will
begin again as previously discussed.
PAUSE allows the user to effectively slow
the rate of data loading through the
LF Interface. When PAUSE is HIGH,
the LF Interfaceis held until PAUSE is
returned LOW. Figure 19 shows the
effects of PAUSE while loading Matrix
Multiplier/Key Scaler coefficients.
Table 28 shows an example of loading a
bias value into the Input Bias Adder
Register. In this example, a bias value of
007FH is loaded into the Channel ‘C’
Input Bias Adder Register 1 (0B01H).
Table 29 shows an example of loading a
bias value into the Output Bias Adder
Register. In this example, a bias value of
0010H is loaded into Channel ‘A’ Output
Bias Adder Register 3 (0903H).
Table 30 shows an example of loading
data into the Matrix Multiplier/Key
Scaler Coefficient Banks. In this example,
the following values are loaded into
Coefficient Register Set 2 (0002H): 0000H,
0001H, 0002H, 0003H, 0004H, 0005H,
0006H, 0007H, 0008H, and 0009H.
Table 31 shows an example of loading the
HF
0
Flag Count Value. In this example, a
20-bit HF
0
Flag Count Value of B3C27H is
loaded into the HF
0
Flag Count Value
Register (0C00H). The HF
1
Flag Count
Value is loaded in the same manner using
the appropriate address.
Table 32 shows an example of loading
Round/Select/Limit values. In this
example, Channel ‘A’ Matrix Multiplier
Register Set 0 (0E00H) is loaded with a 20-
bit Round value of 00020H, a 2-bit Select
value of 10H, a 13-bit Upper Limit value
of 0FFFH, and a 13-bit Lower Limit value
of 1001H. Other RSL registers are loaded
in the same manner using the appropriate
address.
BITS
FUNCTION
DESCRIPTION
1-0
Look-Up Table Control
Channel ‘A’
00 : Disable Look-Up Table
01 : Enable Look-Up Table on Input
10 : Enable Look-Up Table on Output
11 : Reserved
00 : Disable Look-Up Table
01 : Enable Look-Up Table on Input
10 : Enable Look-Up Table on Output
11 : Reserved
00 : Disable Look-Up Table
01 : Enable Look-Up Table on Input
10 : Enable Look-Up Table on Output
11 : Reserved
0 : Disable Horizontal Blanking Option
During HBLANK Period
1 : Enable Horizontal Blanking Option
During HBLANK Period
00 : Output Channel ‘A’ to W
12-0
01 : Output Channel ‘B’ to W
12-0
10 : Output Channel ‘C’ to W
12-0
11 : Output Channel ‘D’ to W
12-0
00 : Select Address Data [9:0]
01 : Select Address Data [10:1]
10 : Select Address Data [11:2]
11 : Select Address Data [12:3]
0 : Enable Input Bias
1 : Disable Input Bias
0 : Enable Output Bias
1 : Disable Output Bias
3-2
Look-Up Table Control
Channel ‘B’
5-4
Look-Up Table Control
Channel ‘C’
6
HBLANK Control
‘Key’ Channel
8-7
Data Bypass Mode ‘W’
Output Channel Mux Control
10-9
Look-Up Table Input
Address Selection Control
11
Input Bias Disable
12
Output Bias Disable
T
ABLE
6.
C
ONFIGURATION
R
EGISTER
1 – A
DDRESS
201H
BITS
FUNCTION
DESCRIPTION
1-0
Video Input Format
00 : Reserved
01 : Single Channel Interleaved Video
10 : Dual Channel Interleaved Video
11 : 3 Channel Non-Interleaved Video
00 : Reserved
01 : Single Channel Interleaved Video
10 : Dual Channel Interleaved Video
11 : 3 Channel Non-Interleaved Video
0 : Filter Feeds Matrix Multiplier
1 : Matrix Multiplier Feeds Filter
00 : Pass Through Filter
01 : Interpolate
10 : Decimate
11 : Bypass Filter
00 : Pass Through Filter
01 : Interpolate
10 : Decimate
11 : Bypass Filter
0 : Normal Order of Operations
1 : Select First Operation Only
Must be Set to Zero
3-2
Video Output Format
4
Functional Arrangement
6-5
Half-Band Filter Control
Channel ‘B’
8-7
Half-Band Filter Control
Channel ‘C’
9
First Operation Select
12-10
Reserved
T
ABLE
5.
C
ONFIGURATION
R
EGISTER
0 – A
DDRESS
200H
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LF3370QC12 制造商:LOGIC 制造商全稱:LOGIC 功能描述:High-Definition Video Format Converter
LF33AB 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Very low drop voltage regulators with inhibit
LF33ABDT 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
LF33ABDT-TR 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
LF33ABP 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20
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