參數(shù)資料
型號: LF3370
廠商: Logic Devices Incorporated
英文描述: High-Definition Video Format Converter(高清晰度視頻格式轉(zhuǎn)換器)
中文描述: 高清晰度視頻格式轉(zhuǎn)換器(高清晰度視頻格式轉(zhuǎn)換器)
文件頁數(shù): 11/22頁
文件大?。?/td> 256K
代理商: LF3370
DEVICES INCORPORATED
Video Imaging Products
11
LF3370
High-Definition Video Format Converter
08/21/2000–LDS.3370-E
Once an impulse is clocked into the Half-
Band Filter section, the 55-value output
response begins after 8 clock cycles and
ends after 62 clock cycles. The pipeline
latency from the input of an impulse to its
corresponding output peak is 35 clock
cycles.
The input/output formats are always in
two’s complement format as shown in
Figure 3. In Interpolate Mode, the gain of
the Half-Band Filter is halved (due to half
of the input samples being padded with
zeros). A right shifted Select window is
required to maintain an overall filter gain
of 1. It is possible that ringing on the
filter’s output could cause the high order
bit (bit F18 in Figure 3 - Interpolate Filter
Output Bit Weighting) to become HIGH.
If a right shifted Select window is used,
this F18 bit becomes the sign bit of the
Selected window – and the output is
erroneously considered negative. To
ensure that no overflow conditions occur,
an internal Limiter within each Half-Band
Filter monitors its output. During
Interpolate mode, this Limiter clamps the
output word to 3FFFFH (20-bit maximum
positive value
)
2) or C0000H (20-bit
maximum negative value
)
2) if a positive
or negative overflow occurs respectively.
The internal 24-bits of the Half-Band Filter
are truncated to 20-bits and then passed to
the Round section of the RSL circuitry; see
RSL section for further details. This
section is fully bypassable by use of
programmable delays (see Bypass
Options section for further details).
Look-Up Table
Three optional programmable Input/
Output 1K x 13-bit LUTs have been
provided for Channels A, B, and C for
various uses such as Gamma Correction.
There are NOT actually two LUTs per
channel as shown in Figures 1 and 2; only
one LUT per channel can be selected for
use at any given time. The latency
through a LUT section is 2 cycles, regard-
less of whether the LUT is in use or not.
When using a LUT, the appropriate
addressed value will be passed as an
output of the LUT section. The Gamma
LUT address can be chosen from any of
the 4 possible10-bit words that are
‘window’ selected from the13-bit Input
data bus. Configuring the desired LUT
address selector position is accomplished
by programming bits 10 & 9 of Configura-
tion Register 1. Once the LUT Select Data
position is programmed, it is meant to
control all three Gamma LUTs. Therefore,
the address selector positions of the three
LUTs cannot be independently controlled.
LUT loading is discussed in the LF
Interface section.
T
ABLE
2.
S
ELECT
F
ORMATS
SLCT
1-0
S
12
S
11
S
10
S
9
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
00
F
16
F
15
F
14
F
13
F
12
F
11
F
10
F
9
F
8
F
7
F
6
F
5
F
4
01
F
17
F
16
F
15
F
14
F
13
F
12
F
11
F
10
F
9
F
8
F
7
F
6
F
5
10
F
18
F
17
F
16
F
15
F
14
F
13
F
12
F
11
F
10
F
9
F
8
F
7
F
6
11
F
19
F
18
F
17
F
16
F
15
F
14
F
13
F
12
F
11
F
10
F
9
F
8
F
7
F
IGURE
14.
F
REQUENCY
R
ESPONSE
OF
F
ILTER
0
0.1
S
0.2
S
0.3
S
0.4
S
0.5
S
FREQUENCY (NORMALIZED)
0
–10
–20
–30
–40
–50
–60
–70
–80
G
F
IGURE
13. RSL C
IRCUITRY
LL0
LL3
R0
R3
ROUND
S0
S3
SELECT
UL0
UL3
20
13
13
LIMIT
2
20
13
20
13
RSL
1-0
From Core
13
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