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參數(shù)資料
| 型號： | LF3370 |
| 廠商： | Logic Devices Incorporated |
| 英文描述： | High-Definition Video Format Converter(高清晰度視頻格式轉(zhuǎn)換器) |
| 中文描述： | 高清晰度視頻格式轉(zhuǎn)換器（高清晰度視頻格式轉(zhuǎn)換器） |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 256K |
| 代理商： | LF3370 |
DEVICES INCORPORATED
LF3370
High-Definition Video Format Converter
12
08/21/2000–LDS.3370-E
Video Imaging Products
Rounding
The rounding circuitry found in the
Matrix Multiplier and Half-Band Filter
sections work in the same manner. The
truncated 20 MSBs from the Matrix
Multiplier or Half-Band Filter output may
be rounded by being added to the
contents of one of the four Round Regis-
ters (see Figure 13). Each round register is
20 bits wide and user-programmable.
This allows the Matrix Multiplier’s or
Half-Band Filter’s output to be rounded to
any precision required. RSL
1-0
deter-
mines which of the four Round Registers
are used in each Rounding Circuitry. A
value of 00 on RSL
1-0
selects Round
Register 0. A value of 01 selects Round
Register 1 and so on. RSL
1-0
may be
changed every clock cycle if desired. If
rounding is not desired, the user must
load and select a Round Register with
value of 0. Round Register loading is
discussed in the LF Interface section.
Selecting
The selecting circuitry found in the Matrix
Multiplier and Half-Band Filter sections
work in the same manner. The output
word of the Matrix Multiplier and Half-
Band Filter feeding the RSL circuitry is the
20 MSBs. However, only 13 bits may be
sent to the next section. Therefore, the
Select Register determines which 13-bits
are passed. There are four select registers;
RSL
1-0
determines which of the four
Select Registers are used in each Select
Circuitry (see Table 2). A value of 00 on
RSL
1-0
selects Select Register 0. A value of
01 selects Select Register 1 and so on.
RSL
1-0
may be changed every clock cycle
if desired. This allows the 13-bit window
to be changed every clock cycle. Select
Register loading is discussed in the
LF Interface section.
Limiting
The Limiting Circuitry found in the
Matrix Multiplier and Half-Band Filter
sections work in the same manner. The
Limit Registers determine the valid range
Impulse Response Out (Non-Interpolated Bit Weighing)
20-bit (MSB) Filter Out (HEX)
FFE35
0
002D2
0
FFB5C
0
00725
0
FF508
0
00F95
0
FEA10
0
01E59
0
FD6A8
0
0393E
0
FAF1B
0
0798D
0
F2BD2
0
28B30
401BC
TAP
1, 55
2, 54
3, 53
4, 52
5, 51
6, 50
7, 49
8, 48
9, 47
10, 46
11, 45
12, 44
13, 43
14, 42
15, 41
16, 40
17, 39
18, 38
19, 37
20, 36
21, 35
22, 34
23, 33
24, 32
25, 31
26, 30
27, 29
28 (center)
Decimal Equivalent
–0.0008755
0
0.0013771
0
–0.00226593
0
0.0034885
0
–0.0053558
0
0.0076084
0
–0.01071167
0
0.0148182
0
–0.02018738
0
0.0279503
0
–0.0394993
0
0.05935097
0
–0.10360334
0
0.3179626
0.500846862
T
ABLE
3.
H
ALF
-B
AND
F
ILTER
I
MPULSE
R
ESPONSE
of output values for each of these two
sections. There are four 13-bit Limit
Registers for each section. RSL
1-0
deter-
mines which of the four Limit Registers
are used in each Limiting Circuitry (see
Figure 13). A value of 00 on RSL
1-0
selects
Limit Register 0. A value of 01 selects
Limit Register 1 and so on.
Each Limit Register contains an upper
and lower limit value. If the value fed to
the Limiting Circuitry is less than the
lower limit, the lower limit value is passed
as the Matrix Multiplier section’s or Half-
Band filter section’s output. If the value
fed to the Limiting Circuitry is greater
than the upper limit, the upper limit value
is passed as the Matrix Multiplier section’s
or Half-Band filter section’s output.
RSL
1-0
may be changed every clock cycle
if desired thus allowing the limit range to
be changed every clock cycle. When
loading limit values into the device, the
upper limit must be greater than the
lower limit. The most negative and most
positive values you can load into the
Limit Registers are 0FFFH and 1000H.
Limit Register loading is discussed in the
LF Interface section.
LF Interface
The LF Interface is used to load the
Configuration Registers, Matrix Multi-
plier/Key Scaler Coefficient Banks, Look-
Up Tables, Input/Output Bias registers,
RSL registers, HF
0
and HF
1
Count Values,
and Horizontal Blanking Levels.
LD is used to enable and disable the
LF Interface. When LD goes low, the
LF Interface is enabled for data input.
The first value fed into the interface on
CF
12-0
is an address which determines
what the interface is going to load (see
Table 4). For example, to load address
Bias Adder Register 2 of the channel B
Output Bias Adder, the first data value
into the LF Interface should be 0A02H.
To load RSL Register 1 for the Keyscaler
RSL, the first data value should be 1101H.
The first address value should be loaded
into the interface on the same clock cycle
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| LF3370QC12 | 制造商:LOGIC 制造商全稱:LOGIC 功能描述:High-Definition Video Format Converter |
| LF33AB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Very low drop voltage regulators with inhibit |
| LF33ABDT | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LF33ABDT-TR | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LF33ABP | 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V 0.5A Positive RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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