參數(shù)資料
型號(hào)： KS9245
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Automated CD-ROM Controller(光盤驅(qū)動(dòng)器控制器器)
中文描述： 自動(dòng)CD - ROM控制器（光盤驅(qū)動(dòng)器控制器器）
文件頁數(shù)： 8/102頁
文件大?。?/td> 419K
代理商： KS9245
SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
1-8
All data blocks are linearly arranged without separating as auxiliary or data block. With the straight
addressing mechanism, firmware overhead and programming mistakes are minimized.
Multiple Block Transfer support
Multiple Block Transfer is supported by the KS9245. The transfer block is specified in the
Current Host
Transfer Block Length Registers
(18h, 19h). For Multiple Block Transfers, up to 256 blocks, or 512K
bytes, can be burst to the host without firmware intervention. In the ATAPI specification, the maximum
host transfer in a single DRQ packet is 64K bytes. The KS9245 will send the maximum number of bytes
in a DRQ packet transfer.
Automated transfer for entire Read command
The KS9245, with its advanced hardware CD Cache Manager, supports host transfers for entire Read or
Read CD commands of up to 64K blocks
,
or 128M bytes, without firmware intervention. When the
ACachE
bit in the
Transfer Sequence Command Register
(0Fh, bit 7) is set
,
the CD Cache Manger is
enabled. At the completion of the total transfers specified in the
Total Host Transfer Block Length
Registers
(16h, 17h), the ATAPI completion status will be posted to the host if the
ACplE
bit in the
Transfer Sequence Command Register
(0Fh, bit 6) is set. Also, the
TxfrDone
bit in the
Host Interrupt
Status Register
(10h, bit 7) will be set and a microprocessor interrupt will be generated if the
TxfrDoneE
bit in the
Host Interrupt Mask Register
(12h, bit 7) is set.
Scatter/Gather Support
The KS9245 provides two sets of segment registers which specify the start offset address and the
transfer byte lengths within a data block. When the transfer is completed in the first segment, the
hardware will automatically chain the second segment and continue the host transfers. The advantage to
using Scatter/Gather feature is to avoid breaking transfer into two or more sub-transfers if data is
scattered within a block. Two segment registers are specified in the
Transfer Offset Length Low/High 1/2
(1Eh, 1Fh, 22h, 23h) and
Host Block Offset Address Low/High 1/2 Registers
(1Ch, 1Dh, 20h, 21h)
.
In a
Read CD command, the host requested data may not be in a contiguous location. For example, the
2048-byte data block and 294-byte C2PO error flags are requested in the same transfer. The firmware
can utilize this Scatter/Gather feature to chain these transfers together.
CD Cache Manager
A hardware CD Cache Manager is supported in KS9245. When the
ACachE
bit in the
Transfer Sequence
Command Register
(0Fh, bit 7) is set, the CD Cache Manager initiates the host transfer as soon as data
is available in the cache. That is, the
Valid Cache Block Count Registers
(14h, 15h) are not equal to
zero, until the
Total Host Transfer Block Length Registers
(16h, 17h) is decreased to zero
.
The host
transfer process is continuously monitored by hardware until all data are transferred.
Block Address support
All data blocks can be addressed by a sequential block number which starts from zero at the top of the
buffer DRAM and ends at the last or bottom of the block address specified in the
Buffer Bottom Block
Address Register
(2Ch). Before starting host transfers, the
Host Transfer Block Address Low/High
Registers
(1Ah, 1Bh) must be loaded with the starting block address. Before starting the decoder
transfers, the
Disk Transfer Block Address Register
(38h) must be loaded with the starting block address.
Both host and disk address pointers are automatically increased by one when a block of data is
transferred to host or from the disk. When these registers reach the values of
Buffer Bottom Block
Address Register
plus one, they are wrapped around to the top of the buffer DRAM.
Microprocessor Physical and Block access DRAM support
Both the physical and block addressing modes for accessing DRAM by the microprocessor are
supported. The
PAMb
bit in the
Buffer Access Control Register
(29h, bit 2) is used to specify the
addressing mode. Using Physical Address Mode (PAM), the DRAM physical address must be loaded into
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