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參數(shù)資料
| 型號： | KS9245 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Automated CD-ROM Controller(光盤驅(qū)動器控制器器) |
| 中文描述： | 自動CD - ROM控制器（光盤驅(qū)動器控制器器） |
| 文件頁數(shù)： | 100/102頁 |
| 文件大?。?/td> | 419K |
| 代理商： | KS9245 |
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SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
12-7
Table 2 lists a subset of the KS9245’ s registers used for configuring CAV mode playback.
Detailed descriptions of these registers can be referenced in the KS9245 ATAPI Automated CD-
ROM Controller Engineering Specification, available from IML.
Valid Audio Block Count Registers (VABC at 48h):
This register specifies the number of valid
audio blocks buffered into DRAM which are available for audio playback. Firmware must
increment this register by one (to keep track of the audio block count) by writing a “1” to the
IncAudCnt
bit in the
Buffer Access Control Register
(Reg29h, bit7) after a decoder interrupt
occurs in Audio Buffering Mode. This register is automatically decremented by one after one audio
block has been output to the AWCK/ABCK/ADAT pins during CAV playback.
Note that a DAC
interrupt is generated after one audio block is output to the AWCK/ABCK/ADAT pins. Aslo, when
this occurs, the
DACInt
bit in the
Decoder Interrupt Status Register
(Reg11h, bit2) is set if the
DACIntE
bit in the
Decoder Interrupt Mask Register
(Reg13h, bit2) is set.
DAC Block Address Register (DABA at 4Ah):
This register points to the audio block in DRAM to
be output or currently being output to the audio DAC. This register is automatically incremented to
point to the next audio block to be played once the current block is completely outputted.
Note that
this pointer will wrap around after the bottom of the buffer is reached.
DAC Output Format Selection Register (DOFS at 4Ch):
This register is used to select various
audio output interface formats for CAV mode playback only. Table 3 lists the available formats
using this register.
Audio Output Format Selection Summary
ABCKD1
AFPS
0
0
0
0
1
1
1
1
Table 3: Audio Output Format Selection
Audio Format
EIAJ 16 bit
EIAJ 18 bit
I2S 16 bit
I2S 18 bit
ADAT18
0
1
0
1
ABCKL
10
10
10
10
ALSBF
0
0
0
0
ALCH
1
1
0
0
ABCKF
0
0
0
0
hex
12h
92h
70h
F0h
In addition, the KS9245 also supports an Audio Bypass mode where it allows inputs from DSP
devices (such as Toshiba, Sanyo, and Sony) to be directly output to the AWCK / ABCK / ADAT
pins without any conversions. This mode is set when the
ABPS
(Audio Bypass Mode) bit is set to
“1” in the
Audio Clock Control Register
(Reg4Eh, bit 6).
DAC Control Register (DACR at 4Dh):
This register is used to control various DAC output
operations such as muting, mono / stereo / swap modes, and start play audio. Bit 7 and Bit 6
control the Left and Right Audio Channel muting for CAV and Audio Bypass modes, except for
DAU Audio Bypass. When any of these bits are set to “1” in CAV or Audio Bypass modes, the
corresponding audio channel is muted. When any of these bits are reset to “0”, the corresponding
audio channel is enabled. Following power-on, software reset, or ATAPI reset conditions, the state
of these bits are set to “1” and both audio channels are muted. Table 4 summarizes the mono /
stereo / swapped modes selected by bits 2 and 1.
Audio Channel Mode Selection
Description
Output both left and right channels
Output right channel data to both channels
Output left channel data to both channels
Left and Right channels data swap
Table 4: Audio Channel Mode Selection
Bit 2, Bit 1
00
01
10
11
Channel Mode
Stereo
Mono Right
Mono Left
Channel Swap
Valid
CAV & Audio Bypass
CAV Only
CAV Only
CAV & Audio Bypass
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