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參數(shù)資料
| 型號： | KS9245 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Automated CD-ROM Controller(光盤驅(qū)動器控制器器) |
| 中文描述： | 自動CD - ROM控制器（光盤驅(qū)動器控制器器） |
| 文件頁數(shù)： | 40/102頁 |
| 文件大?。?/td> | 419K |
| 代理商： | KS9245 |
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SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
4-2
Register 11h:
Decoder Interrupt Status Register (Read)
Decoder Interrupt Clear Register (Write)
DISR/DICR
BIT 5
BIT 4
BIT 3
Reserved
Acronym:
BIT 7
BIT 6
BIT 2
DACInt
BIT 1
SubInt
BIT 0
DecInt
This register informs the firmware of various CD decoder interrupts reported by the KS9245.
Writing a “1” to any bit clears that respective interrupt. Writing a “0” to any bit causes no change
for that respective interrupt.
Bit 7-3: Reserved
These bits are reserved for future enhancements.
Bit 2: DACInt (Audio DAC Output Interrupt)
This
bit is set when one block of audio data (2352 byte) is output to the external audio DAC via the
AWCK/ABCK/ADAT pins.
Bit 1: SubInt (CD Subcode Interrupt)
This bit is set when the CD Subcode interrupt occurs.
Bit 0: DecInt (CD Decoder Interrupt)
This
bit is set when a CD decoder interrupt occurs.
Register 12h:
Host Interrupt Mask Register (Read)
Host Interrupt Mask Register (Write)
HIM
BIT 5
BIT 4
CxfrDone
E
Acronym:
BIT 7
TxfrDoneE
BIT 6
BIT 3
HrstE
BIT 2
ScmdRcvE
BIT 1
AcmdRcvE
BIT 0
PcmdRcvE
AsrstE
SrstE
This register controls the masking for each interrupt source. Writing a “1” to each bit enables the
interrupt for that corresponding function. Writing a “0” to each bit, disables the interrupt for that
corresponding function.
Bit 7: TxfrDoneE (Total Host Request Transfer Done Enable)
When this bit is set, the
TxfrDone
interrupt (10h, bit 7) is enabled. When this bit is reset, the
TxfrDone
interrupt is disabled.
Bit 6: CxfrDoneE (Host Block Transfer Done Interrupt Enable)
When this bit is set, the
CxfrDone
interrupt (10h, bit 6) is enabled. When this bit is reset, the
CxfrDone
interrupt is disabled.
Bit 5: AsrstE (ATAPI Soft Reset Command Interrupt Enabled)
When this bit is set, the
Asrst
interrupt (10h, bit 5) is enabled. When this bit is reset, the
Asrst
interrupt is disabled.
Bit 4: SrstE(ATA SRST Reset Interrupt Enabled)
When this bit is set, the
Srst
interrupt (10h, bit 4) is enabled. When this bit is reset, the Srst
interrupt is disabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KS9246 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:ATAPI AUTOMATED CD-ROM CONTROLLER WITH EMBEDDED DRAM |
| KS926S2 | 制造商:FUJI 制造商全稱:Fuji Electric 功能描述:LOW LOSS SUPER HIGH SPEED RECTIFIER |
| KS926S2_07 | 制造商:FUJI 制造商全稱:Fuji Electric 功能描述:LOW LOSS SUPER HIGH SPEED RECTIFIER |
| KS9282B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:CMOS INTEGRATED CIRCUIT |
| KS9286 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR for CDP |
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