參數資料
型號: KS9245
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Automated CD-ROM Controller(光盤驅動器控制器器)
中文描述: 自動CD - ROM控制器(光盤驅動器控制器器)
文件頁數: 11/102頁
文件大?。?/td> 419K
代理商: KS9245
SAMSUNG
Version: TM 2.4
KS9245 ATAPI Automated CD-ROM Controller
Preliminary Technical Manual
_____________________________________________________________
Do Not Copy or Release
1-11
is guaranteed to be smoothly concatenated without losing audio frames during CAV playback. In the
KS9245, up to 50X CAV operation in outer tracks is supported.
The buffered audio data is output to the external audio DAC at 44.1Khz (Word Clock) in either EIAJ or
I2S audio formats regardless of the disk speed. Also, the audio data underrun condition is masked by
muting both output channels to guard against undesired audio noise. As results, in CAV applications, the
audio playback can be achieved by CD-ROM controller in a low cost design.
In order to simplify firmware efforts and efficiently control the audio playback sequences, the Audio
Hardware Buffer Manager implemented will automatically keep track of the available audio block(s) in
buffer DRAM. When this buffer is full, firmware is able to stop the DSP buffering operation. If the buffer
is empty or underrun, the audio mute operation is automatically performed by hardware to avoid any
noise from being outputted.
The audio output pins can be selected and configured via the AWCK, ABCK, ADAT and EBUO pins. The
clock source is derived directly from the system clock thus eliminating the need for another crystal for
the audio clock.
Repeated Correction support
Repeated correction is supported by the KS9245 for intensively non real-time correction environments.
By setting the appropriate
Disk Transfer Block Address Registers
(38h, 39h) and writing a one in the
RepCorr
bit in the
ECC Control 2 Register
(3Ch, bit 2), the correction is started. An interrupt will be
generated with the
DecInt
bit set in the
Decoder Interrupt Status Register
(11h, bit 0) if the
DecIntE
bit in
Decoder Interrupt Mask Register
(13h, bit 0) is set.
Sync Mark Insertion support
The Sync Mark insertion is supported by the KS9245. When the decoder is in the ECC, Buffering Only
Mode, or Monitor Mode, the Sync Insertion logic is active. This allows the DSP Interface logic to recover
from lost synchronization errors. If the decoder is in the Monitor Mode, the Sync Insertion logic will
always re-synchronize with the most recent Sync Mark to insure that synchronization is never lost.
Q-Subcode deinterleave with CRC check support
The 12-byte de-interleaved Q subcode is supported by the KS9245. The de-interleaved Q subcode data
with four zeros data are written into buffer DRAM without firmware intervention. Also, the CRC check for
Q subcode is done by hardware and this CRC result is reported in the
Subcode Status Register
(41h, bit
7, 6) when a subcode interrupt occurs.
Real-time ECC and Sector Synchronized method support
ECC operation starts as soon as the previous block has finished buffering operation with EDC error. The
ECC operation is synchronized with the sector sync pattern. As a result, the data block address for ECC
operation is always one block behind the DSP buffering operation. Because of the sector synchronized
architecture of ECC corrections, blocks are processed in real-time. In other “buffered data correction” or
“delayed pipeline ECC correction” methods, the buffer DRAM will quickly fill when some erroneous
blocks occur. As a result, a consequent seek may be required. Therefore, the real-time ECC correction
of the KS9245 offers a superior correction scheme to other methods.
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