參數(shù)資料
型號: ISP1761BE,518
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 94/164頁
文件大小: 767K
代理商: ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
34 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Specication for
8.1.4 HCCPARAMS register
The Host Controller Capability Parameters (HCCPARAMS) register is a 4 bytes register,
and the bit allocation is given in Table 13.
Bit
23
22
21
20
19
18
17
16
Symbol
DPN[3:0]
reserved
P_INDICAT
OR
Reset
00000000
Access
RRRRRRRR
Bit
15
14
13
12
11
10
9
8
Symbol
N_CC[3:0]
N_PCC[3:0]
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
PRR
reserved
PPC
N_PORTS[3:0]
Reset
00010001
Access
RRRRRRRR
Table 12.
HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit
description
Bit
Symbol
Description[1]
31 to 24
-
reserved; write logic 0
23 to 20
DPN[3:0]
Debug Port Number: This eld identies which of the host controller
ports is the debug port.
19 to 17
-
reserved; write logic 0
16
P_INDICATOR
Port Indicators: This bit indicates whether the ports support port
indicator control.
15 to 12
N_CC[3:0]
Number of Companion Controller: This eld indicates the number
of companion controllers associated with this Hi-Speed USB host
controller.
11 to 8
N_PCC[3:0]
Number of Ports per Companion Controller: This eld indicates the
number of ports supported per companion host controller.
7
PRR
Port Routing Rules: This eld indicates the method used to map
ports to the companion controllers.
6 to 5
-
reserved; write logic 0
4
PPC
Port Power Control: This eld indicates whether the host controller
implementation includes port power control.
3 to 0
N_PORTS[3:0] N_Ports: This eld species the number of physical downstream
ports implemented on this host controller.
Table 13.
HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
RRRRRRRR
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