參數(shù)資料
型號(hào)： ISP1761BE,518
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 7/164頁
文件大小： 767K
代理商： ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
103 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
In 32-bit bus access mode, the register addresses are 4 bytes aligned. Therefore, the
DcBufferStatus register can be accessed using the upper-two bytes of the Buffer
Length register.
The SOFTCT bit in the Mode register has been removed. The DP_PULLUP control bit
in the OTG Control register is used in the ISP1761 in place of the SOFTCT bit in the
ISP1582.
Added the Interrupt Pulse Width register to dene the pulse width of the interrupt
signal.
10.4.2 ISP1761 DMA
DMA mode 1 and DMA mode 2 in the ISP1582 are not supported in the ISP1761.
In DMA mode 0, counter mode is supported and external-EOT mode has been
removed.
Supports the 16-bit and 32-bit DMA. Does not support the 8-bit DMA.
The RD_N and WR_N signals are available for the DMA data strobe. These signals
are also used as data strobe signals during the PIO access. An internal multiplex will
redirect these signals to the DMA controller for the DMA transfer or to registers for the
PIO access.
For details on the DMA programming, refer to application note Ref. 7 “ISP1761 Peripheral
10.4.3 ISP1761 peripheral suspend indication
A HIGH level on the DC_SUSPEND/WAKEUP_N pin indicates that the peripheral has
entered suspend mode. The pulse indication mode has been removed.
10.4.4 ISP1761 interrupt and DMA common mode
In common mode, the interrupt and DMA signals of the peripheral controller are redirected
to pins that are used by the host controller because the host controller and the peripheral
controller share the same pins. Some control bits must be set in the HW Mode Control
register, see Section 8.3.1.
10.5 Peripheral controller-specic registers
Table 97.
Peripheral controller-specic register overview
Address
Register
Reset value
References
Initialization registers
0200h
Address
00h
020Ch
Mode
0000h
0210h
Interrupt Conguration
FCh
0212h
Debug
0008h
0214h
DcInterruptEnable
0000 0000h
0300h
HW Mode Control
0000 0000h
0374h
OTG Control
0000 0086h
Data ow registers
022Ch
Endpoint Index
20h
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