參數(shù)資料
型號： ISP1761BE,518
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 116/164頁
文件大小： 767K
代理商： ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
54 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
Bit
7
6
5
4
3
2
1
0
Symbol
INT_IRQ
CLK
READY
HCSUSP
reserved[1]
DMAEOT
INT
reserved[1]
SOFITLINT
reserved[1]
Reset
00000000
Access
R/W
Table 54.
HcInterrupt - Host Controller Interrupt register (address 0310h) bit
description
Bit
Symbol
Description
31 to 11 -
reserved; write reset value
10
OTG_IRQ
OTG_IRQ: Indicates that an OTG event occurred. The IRQ line will be
asserted if the respective enable bit in the HcInterruptEnable register is
set.
0 — No OTG event
1 — OTG event occurred
For details, see Section 7.4.
9
ISO_IRQ
ISO IRQ: Indicates that an ISO PTD was completed, or the PTDs
corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ
Mask OR register bits combination were completed. The IRQ line will be
asserted if the respective enable bit in the HcInterruptEnable register is
set.
0 — No ISO PTD event occurred
1 — ISO PTD event occurred
For details, see Section 7.4.
8
ATL_IRQ
ATL IRQ: Indicates that an ATL PTD was completed, or the PTDs
corresponding to the bits set in the ATL IRQ Mask AND or ATL IRQ
Mask OR register bits combination were completed. The IRQ line will be
asserted if the respective enable bit in the HcInterruptEnable register is
set.
0 — No ATL PTD event occurred
1 — ATL PTD event occurred
For details, see Section 7.4.
7
INT_IRQ
INT IRQ: Indicates that an INT PTD was completed, or the PTDs
corresponding to the bits set in the INT IRQ Mask AND or INT IRQ
Mask OR register bits combination were completed. The IRQ line will be
asserted if the respective enable bit in the HcInterruptEnable register is
set.
0 — No INT PTD event occurred
1 — INT PTD event occurred
For details, see Section 7.4.
6
CLKREADY
Clock Ready: Indicates that internal clock signals are running stable.
The IRQ line will be asserted if the respective enable bit in the
HcInterruptEnable register is set.
0 — No CLKREADY event has occurred
1 — CLKREADY event occurred
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