參數(shù)資料
型號： ISP1761BE,518
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 5/164頁
文件大?。?/td> 767K
代理商： ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
101 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
If bit INT_EOT in the DMA Interrupt Reason register is set, it indicates that a short or
empty packet is received. This means that DMA transfer terminated. Normally, for an OUT
transfer, it means that remote host wishes to terminate the DMA transfer.
If both the bits DMA_XFER_OK and INT_EOT are set, it means that the transfer counter
reached zero and the last packet of the transfer is a short packet. Therefore, the DMA
transfer is successfully stopped.
Setting bit GDMA Stop in the DMA Command register (address: 0230h) will force the
DMA to stop and bit GDMA_STOP in the DMA Interrupt Reason register (address: 0250h)
will be set to indicate this event.
Setting bit Reset DMA in the DMA Command register (address: 0230h) will force the DMA
to stop and initialize the DMA core to its power-on reset state.
10.2 Endpoint description
Each USB peripheral is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication ow between the USB host and the USB
peripheral. At design time, each endpoint is assigned a unique endpoint identier; see
Table 96. The combination of the peripheral address (given by the host during
enumeration), the endpoint number, and the transfer direction allows each endpoint to be
uniquely referenced.
The peripheral controller has 8 kB of internal FIFO memory, which is shared among the
enabled USB endpoints. The two control endpoints are xed 64 bytes long. Any of the
seven IN and seven OUT endpoints can separately be enabled or disabled. The endpoint
type (interrupt, isochronous or bulk) and packet size of these endpoints can individually be
congured, depending on the requirements of the application. Optional double buffering
increases the data throughput of these data endpoints.
Table 96.
Endpoint access and programmability
Endpoint
identier
Maximum packet
size
Double buffering Endpoint type
Direction
EP0SETUP
8 bytes (xed)
no
set-up token
OUT
EP0RX
64 bytes (xed)
no
control OUT
OUT
EP0TX
64 bytes (xed)
no
control IN
IN
EP1RX
programmable
yes
programmable
OUT
EP1TX
programmable
yes
programmable
IN
EP2RX
programmable
yes
programmable
OUT
EP2TX
programmable
yes
programmable
IN
EP3RX
programmable
yes
programmable
OUT
EP3TX
programmable
yes
programmable
IN
EP4RX
programmable
yes
programmable
OUT
EP4TX
programmable
yes
programmable
IN
EP5RX
programmable
yes
programmable
OUT
EP5TX
programmable
yes
programmable
IN
EP6RX
programmable
yes
programmable
OUT
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ISP1761BEUM 功能描述:IC USB OTG CONTROLLER HS 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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