參數(shù)資料
型號(hào): ISP1761BE,518
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 74/164頁
文件大?。?/td> 767K
代理商: ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
16 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
Port 2 does not need to be enabled using software if only port 1 or port 3 is used. No port
needs to be disabled by external pull-up resistors, if not used. The DP and DM of the
unused ports need not be externally pulled HIGH because there are internal pull-down
resistors on each port that are enabled by default.
Table 3 lists the various port connection scenarios.
7.2 Host controller buffer memory block
7.2.1 General considerations
The internal addressable host controller buffer memory is 63 kB. The 63 kB effective
memory size is the result of subtracting the size of the registers (1 kB) from the total
addressable memory space dened by the ISP1761 (64 kB). This is an optimized value to
achieve the highest performance with minimal cost.
The ISP1761 is a slave host controller. This means that it does not need access to the
local bus of the system to transfer data from the system memory to the ISP1761 internal
memory, unlike the case of the original PCI Hi-Speed USB host controllers. Therefore,
correct data must be transferred to both the Philips Transfer Descriptor (PTD) area and
the payload area by PIO (using CPU access) or programmed DMA.
The ‘slave-host’ architecture ensures better compatibility with most of the processors
present in the market today because not all processors allow a ‘bus-master’ on the local
bus. It also allows better load balancing of the processor’s local bus because only the
internal bus arbiter of the processor controls the transfer of data dedicated to USB. This
prevents the local bus from being busy when other more important transfers may be in the
queue; and therefore achieving a ‘linear’ system data ow that has less impact on other
processes running at the same time.
The considerations mentioned are also the main reason for implementing the pre-fetching
technique, instead of using a READY signal. The resulting architecture avoids ‘freezing’ of
the local bus, by asserting READY, enhancing the ISP1761 memory access time, and
avoiding introduction of programmed additional wait states. For details, see Section 7.3.
Table 3.
Port connection scenarios
Port conguration
Port 1
Port 2
Port 3
One port (port 1)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are not connected
(left open)
One port (port 2)
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
One port (port 3)
DP and DM are not connected
(left open)
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
Two ports (ports 1
and 2)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
Two ports (ports 2
and 3)
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
Two ports (ports 1
and 3)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
Three ports (ports 1,
2 and 3)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
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