參數(shù)資料
型號: ISP1761BE,518
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 88/164頁
文件大?。?/td> 767K
代理商: ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
2 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
I Separate IRQ, DREQ and DACK lines for the host controller and the peripheral
controller
I Integrated multi-conguration FIFO
I Double-buffering scheme increases throughput and facilitates real-time data transfer
I Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI
I Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V)
I 3.3 V-to-5.0 V external power supply input
I Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for
low-power core)
I Internal power-on reset or low-voltage reset and block-dedicated software reset
I Supports suspend and remote wake-up
I Built-in overcurrent circuitry (analog overcurrent protection)
I Hybrid-power mode: VCC(5V0) (can be switched off), VCC(I/O) (permanent)
I Target total current consumption:
N Normal operation; one port in high-speed active: ICC < 100 mA when the internal
charge pump is not used
N Suspend mode: ICC(susp) < 150 A at ambient temperature of +25 °C
I Available in LQFP128 and TFBGA128 packages
I Host controller-specic features
N High performance USB host with integrated Hi-Speed USB transceivers; supports
high-speed, full-speed and low-speed
N Congurable power management
N Integrated TT for Original USB peripheral support on all three ports
N Integrated 64 kB high-speed memory (internally organized as 8 k × 64 bit)
N Additional 2.5 kB separate memory for TT
N Individual or global overcurrent protection with built-in sense circuits
N Built-in overcurrent circuitry (digital or analog overcurrent protection)
I OTG controller-specic features
N OTG transceiver: fully integrated; adheres to Ref. 3 “On-The-Go Supplement to the
N Supports HNP and SRP for OTG dual-role devices
N HNP: status and control registers for software implementation
N SRP: status and control registers for software implementation
N Programmable timers with high resolution (0.01 ms to 80 ms) for HNP and SRP
N Supports external source of VBUS
I Peripheral controller-specic features
N High-performance USB peripheral controller with integrated Serial Interface Engine
(SIE), FIFO memory and transceiver
class specications
N Supports auto Hi-Speed USB mode discovery and Original USB fallback
capabilities
N Supports high-speed and full-speed on the peripheral controller
N Bus-powered or self-powered capability with suspend mode
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