參數(shù)資料
型號: ISP1761BE,518
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 108/164頁
文件大?。?/td> 767K
代理商: ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
47 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
8.3.6 HcBufferStatus register
The HcBufferStatus register is used to indicate the HC that a particular PTD buffer (that is,
ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets
the Buffer Filled bit of a particular transfer in the HcBufferStatus register, the HC will start
traversing through PTD headers that are not marked for skipping and are valid PTDs.
Remark: Software can set these bits during the initialization.
Table 42 shows the bit allocation of the HcBufferStatus register.
Table 41.
HcDMAConguration - Host Controller Direct Memory Access Conguration
register (address 0330h) bit description
Bit
Symbol
Description
31 to 8 DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read or
write).
Remark: Different number of bursts will be generated for the
same transfer length programmed in 16-bit and 32-bit modes
because DMA_COUNTER is in number of bytes.
7 to 4
-
reserved
3 to 2
BURST_LEN[1:0]
DMA Burst Length:
00 — Single DMA burst
01 — 4-cycle DMA burst
10 — 8-cycle DMA burst
11 — 16-cycle DMA burst
1
ENABLE_DMA
Enable DMA:
0 — Terminate DMA
1 — Enable DMA
0
DMA_READ_WRITE_
SEL
DMA Read or Write Select: Indicates if the DMA operation is a
write or read to or from the ISP1761.
0 — DMA write to the ISP1761 internal RAM is set
1 — DMA read from the ISP1761 internal RAM
Table 42.
HcBufferStatus - Host Controller Buffer Status register (address 0334h) bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
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