- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67723 > ISP1563BM (ST-ERICSSON) UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | ISP1563BM |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100 |
| 文件頁數(shù)： | 82/102頁 |
| 文件大小： | 466K |
| 代理商： | ISP1563BM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁當前第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
80 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
8PR
Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not in reset. Default = 0.
When software sets this bit from logic 0, the bus reset sequence as dened in
Universal Serial
Bus Specication Rev. 2.0 is started. Software clears this bit to terminate the bus reset sequence.
Software must hold this bit at logic 1 until the reset sequence, as specied in
Universal Serial Bus
Specication Rev. 2.0, is completed.
Remark: When software sets this bit, it must also clear the Port Enable bit.
Remark: When software clears this bit, there may be a delay before the bit status changes to
logic 0 because it will not read logic 0 until the reset is completed. If the port is in high-speed
mode after reset is completed, the Host Controller will automatically enable this port; it can set the
Port Enable bit. A Host Controller must terminate the reset and stabilize the state of the port
within 2 ms of software changing this bit from logic 1 to logic 0. For example, if the port detects
that the attached device is high-speed during a reset, then the Host Controller must enable the
port within 2 ms of software clearing this bit.
HCH (bit 12 in the USBSTS register) must be logic 0 before software attempts to use this bit. The
Host Controller may hold Port Reset asserted when the HCH bit is set.[1]
7
SUSP
Suspend: Default = 0. Logic 1 means the port is in the suspend state. Logic 0 means the port is
not suspended. The PED (Port Enabled) bit and this bit dene the port states as follows:
PED = 0 and SUSP = X — Port is disabled.
PED = 1 and SUSP = 0 — Port is enabled.
PED = 1 and SUSP = 1 — port is suspended.
When in the suspend state, downstream propagation of data is blocked on this port, except for the
port reset. If a transaction was in progress when this bit was set, blocking occurs at the end of the
current transaction. In the suspend state, the port is sensitive to resume detection. The bit status
does not change until the port is suspended and there may be a delay in suspending a port, if
there is a transaction currently in progress on USB. Attempts to clear this bit are ignored by the
Host Controller. The Host Controller will unconditionally set this bit to logic 0 when:
Software changes the FPR (Force Port Resume) bit to logic 0.
Software changes the PR (Port Reset) bit to logic 1.
If the host software sets this bit when the Port Enabled bit is logic 0, the results are undened.[1]
6
FPR
Force Port Resume: Logic 1 means resume detected or driven on the port. Logic 0 means no
resume (K-state) detected or driven on the port. Default = 0. Software sets this bit to drive the
resume signaling. The Host Controller sets this bit if a J-to-K transition is detected, while the port
is in the suspend state. When this bit changes to logic 1 because a J-to-K transition is detected,
PCD (bit 2 in register USBSTS) is also set to logic 1. If software sets this bit to logic 1, the Host
Controller must not set bit PCD. When the EHCI controller owns the port, the resume sequence
follows the sequence given in
Universal Serial Bus Specication Rev. 2.0. The resume signaling
(full-speed ‘K’) is driven on the port as long as this bit remains set. Software must time the resume
and clear this bit after the correct amount of time has elapsed. Clearing this bit causes the port to
return to high-speed mode, forcing the bus below the port into a high-speed idle. This bit will
remain at logic 1, until the port has switched to the high-speed idle. The Host Controller must
complete this transition within 2 ms of software clearing this bit.[1]
5
OCC
Overcurrent Change: Default = 0. This bit is set to logic 1 when there is a change in overcurrent
active. Software clears this bit by setting this bit to logic 1.
4
OCA
Overcurrent Active: Default = 0. If set to logic 1, this port has an overcurrent condition. If set to
logic 0, this port does not have an overcurrent condition. This bit will automatically change from
logic 1 to logic 0 when the overcurrent condition is removed.
3
PEDC
Port Enable/Disable Change: Logic 1 means the port enabled or disabled status has changed.
Logic 0 means no change. Default = 0. For the root hub, this bit is set only when a port is disabled
because of the appropriate conditions existing at the EOF2 point. For denition of port error, refer
to
Universal Serial Bus Specication Rev. 2.0, Chapter 11. Software clears this bit by setting it.[1]
Table 119. PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description …continued
Address: Content of the base address register + 64h + (4
× Port Number 1) where Port Number is 1, 2, 3, 4
Bit
Symbol
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1563BM,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| ISP1564ET,551 | PCI BUS CONTROLLER, PBGA100 |
| ISP1582BS,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQCC56 |
| ISP1583ET1,118 | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| ISP1583BS,551 | UNIVERSAL SERIAL BUS CONTROLLER, PQCC64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1563BM,518 | 功能描述:USB 接口集成電路 USB 2.0 4PORT PCI RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1563BM,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1563BM,557 | 功能描述:USB 接口集成電路 USB 2.0 4PORT PCI HOST CONTROL RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1563BM518 | 制造商:ST-Ericsson 功能描述:CONTROLLER USB PCI HOST 128LQFP |
| ISP1563BMGA | 功能描述:IC USB HOST CTRL HI-SPD 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。