參數(shù)資料
型號: ISP1563BM
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù): 24/102頁
文件大?。?/td> 466K
代理商: ISP1563BM
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
28 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
Table 35.
PMC - Power Management Capabilities register bit description
Address: Value read from address 34h + 2h
Bit
Symbol
Description
15 to 11
PME_S[4:0]
PME Support: These bits indicate the power states in which the function may assert PME#.
Logic 0 for any bit indicates that the function is not capable of asserting the PME# signal while in
that power state.
PME_S[0] — PME# can be asserted from D0
PME_S[1] — PME# can be asserted from D1
PME_S[2] — PME# can be asserted from D2
PME_S[3] — PME# can be asserted from D3hot
PME_S[4] — PME# can be asserted from D3cold
10
D2_S
D2 Support: If this bit is logic 1, this function supports the D2 power management state.
Functions that do not support D2 must always return logic 0 for this bit.
9
D1_S
D1 Support: If this bit is logic 1, this function supports the D1 power management state.
Functions that do not support D1 must always return logic 0 for this bit.
8 to 6
AUX_C[2:0]
Auxiliary Current: This three-bit eld reports the Vaux(3V3) auxiliary current requirements for the
PCI function.
If the Data register is implemented by this function:
A read from this eld needs to return a value of 000b.
The Data register takes precedence over this eld for Vaux(3V3) current requirement
reporting.
If the PME# generation from D3cold is not supported by the function (PMC[15] = 0), this eld must
return a value of 000b when read.
For functions that support PME# from D3cold and do not implement the Data register, the bit
assignments corresponding to the maximum current required for Vaux(3V3) are:
111b — 375 mA
110b — 320 mA
101b — 270 mA
100b — 220 mA
011b — 160 mA
010b — 100 mA
001b — 55 mA
000b — 0 (self-powered)
5
DSI
Device Specic Initialization: This bit indicates whether special initialization of this function is
required, beyond the standard PCI conguration header, before the generic class device driver is
able to use it.
This bit is not used by some operating systems. For example, Microsoft Windows and Windows
NT do not use this bit to determine whether to use D3. Instead, it is determined using the
capabilities of the driver.
Logic 1 indicates that the function requires a device-specic initialization sequence, following
transition to D0 uninitialized state.
4
reserved
-
3
PMI
PME Clock:
0 — Indicates that no PCI clock is required for the function to generate PME#.
1 — Indicates that the function relies on the presence of the PCI clock for the PME# operation.
Functions that do not support the PME# generation in any state must return logic 0 for this eld.
2 to 0
VER[2:0]
Version: A value of 010b indicates that this function complies with
PCI Power Management
Interface Specication Rev. 1.1.
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