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| 型號： | ISP1563BM |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100 |
| 文件頁數(shù)： | 17/102頁 |
| 文件大?。?/td> | 466K |
| 代理商： | ISP1563BM |
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ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
21 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
8.2.1.7
CacheLine Size register
The CacheLine Size register is a read and write single-byte register that species the
system CacheLine size in units of DWORDs. This register must be implemented by
master devices that can generate the Memory Write and Invalidate command. The value
in this register is also used by master devices to determine whether to use Read, Read
Line or Read Multiple commands to access the memory.
Slave devices that want to allow memory bursting using CacheLine-wrap addressing
mode must implement this register to know when a burst sequence wraps to the
beginning of the CacheLine.
This eld must be initialized to logic 0 on activation of RST#. Table 13 shows the bit
description of the CacheLine Size register.
8.2.1.8
Latency Timer register
This register species, in units of PCI bus clocks, the value of the latency timer for the PCI
bus master. Table 14 shows the bit description of the Latency Timer register.
8.2.1.9
Header Type register
The Header Type register identies the layout of the second part of the predened header;
beginning at byte 10h in conguration space. It also identies whether the device contains
multiple functions. For bit allocation, see Table 15.
Table 12.
CC - Class Code register (address 09h) bit description
Bit
Symbol
Description
23 to 16
BCC[7:0]
Base Class Code: 0Ch is the base class code assigned to this byte. It implies a serial bus controller.
15 to 8
SCC[7:0]
Sub-Class Code: 03h is the sub-class code assigned to this byte. It implies the USB Host Controller.
7 to 0
RLPI[7:0] Register-Level Programming Interface: 10h is the programming interface code assigned to OHCI,
which is USB 1.1 specication compliant. 20h is the programming interface code assigned to EHCI,
which is USB 2.0 specication compliant.
Table 13.
CLS - CacheLine Size register (address 0Ch) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
CLS[7:0]
R/W
00h*
CacheLine Size: This byte identies the system CacheLine size.
Table 14.
LT - Latency Timer register (address 0Dh) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
LT[7:0]
R/W
00h*
Latency Timer: This byte identies the latency timer.
Table 15.
HT - Header Type register (address 0Eh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
MFD
HT[6:0]
Reset
10000000
Access
RRRRRRRR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1563BM,518 | 功能描述:USB 接口集成電路 USB 2.0 4PORT PCI RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1563BM,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1563BM,557 | 功能描述:USB 接口集成電路 USB 2.0 4PORT PCI HOST CONTROL RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1563BM518 | 制造商:ST-Ericsson 功能描述:CONTROLLER USB PCI HOST 128LQFP |
| ISP1563BMGA | 功能描述:IC USB HOST CTRL HI-SPD 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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