參數(shù)資料
型號(hào)： ISP1563BM
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù)： 50/102頁
文件大?。?/td> 466K
代理商： ISP1563BM
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
51 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
11.1.15 HcFmRemaining register
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in
the current frame.
Table 71 contains the bit allocation of this 4-byte register.
[1]
The reserved bits should always be written with the reset value.
Table 70.
HcFmInterval - Host Controller Frame Interval register bit description
Address: Content of the base address register + 34h
Bit
Symbol
Description
31
FIT
Frame Interval Toggle: The HCD toggles this bit whenever it loads a new value to Frame
Interval.
30 to 16
FSMPS[14:0]
FS Largest Data Packet: This eld species the value that is loaded into the largest data packet
counter at the beginning of each frame. The counter value represents the largest amount of data
in bits that can be sent or received by the Host Controller in a single transaction at any given time,
without causing a scheduling overrun. The eld value is calculated by the HCD.
15 to 14
reserved
-
13 to 0
FI[13:0]
Frame Interval: This species the interval between two consecutive SOFs in bit times. The
nominal value is set to 11,999. The HCD must store the current value of this eld before resetting
the Host Controller to reset this eld to its nominal value. The HCD can then restore the stored
value on completing the reset sequence.
Table 71.
HcFmRemaining - Host Controller Frame Remaining register bit allocation
Address: Content of the base address register + 38h
Bit
31
30
29
28
27
26
25
24
Symbol
FRT
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
FR[13:8]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FR[7:0]
Reset
00000000
Access
R/W
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