參數(shù)資料
型號(hào): ISP1563BM
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù): 40/102頁
文件大?。?/td> 466K
代理商: ISP1563BM
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
42 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
A bit is set in the HcInterruptStatus register.
The corresponding bit in the HcInterruptEnable register is set.
The MIE (Master Interrupt Enable) bit is set.
Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to
a bit in this register leaves the corresponding bit unchanged. On a read, the current value
of this register is returned. The bit allocation is given in Table 51.
[1]
The reserved bits should always be written with the reset value.
Table 51.
HcInterruptEnable - Host Controller Interrupt Enable register bit allocation
Address: Content of the base address register + 10h
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
OC
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
RHSC
FNO
UE
RD
SF
WDH
SO
Reset
00000000
Access
R/W
Table 52.
HcInterruptEnable - Host Controller Interrupt Enable register bit description
Address: Content of the base address register + 10h
Bit
Symbol
Description
31
MIE
Master Interrupt Enable:
0 — Ignore
1 — Enables interrupt generation by events specied in other bits of this register.
30
OC
Ownership Change:
0 — Ignore
1 — Enables interrupt generation because of ownership change.
29 to 7
reserved
-
6
RHSC
Root Hub Status Change:
0 — Ignore
1 — Enables interrupt generation because of root hub status change.
5
FNO
Frame Number Overow:
0 — Ignore
1 — Enables interrupt generation because of frame number overow.
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