參數(shù)資料
型號: ISP1563BM
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù): 36/102頁
文件大?。?/td> 466K
代理商: ISP1563BM
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
39 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
11.1.3 HcCommandStatus register
This register is used by the Host Controller to receive commands issued by the HCD. It
also reects the current status of the Host Controller. To the HCD, it appears as a ‘write to
set’ register. The Host Controller must ensure that bits written as logic 1 become set in the
register while bits written as logic 0 remain unchanged in the register. The HCD may issue
multiple distinct commands to the Host Controller without concern for corrupting
previously issued commands. The HCD has normal read access to all bits.
The SOC[1:0] eld (bits 17 and 16 in the HcCommandStatus register) indicates the
number of frames with which the Host Controller has detected the scheduling overrun
error. This occurs when the periodic list does not complete before EOF. When a
scheduling overrun error is detected, the Host Controller increments the counter and sets
SO (bit 0 in the HcInterruptStatus register). For bit allocation, see Table 47.
[1]
The reserved bits should always be written with the reset value.
1 to 0
CBSR[1:0]
Control Bulk Service Ratio: This species the service ratio of control EDs over bulk EDs.
Before processing any of the nonperiodic lists, the Host Controller must compare the ratio
specied with its internal count on how many nonempty control EDs are processed, in
determining whether to continue serving another control ED or switch to bulk EDs. The internal
count must be retained when crossing the frame boundary. After a reset, the HCD is responsible
to restore this value.
00b — 1 : 1
01b — 2 : 1
10b — 3 : 1
11b — 4 : 1
Table 46.
HcControl - Host Controller Control register bit description …continued
Address: Content of the base address register + 04h
Bit
Symbol
Description
Table 47.
HcCommandStatus - Host Controller Command Status register bit allocation
Address: Content of the base address register + 08h
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
SOC[1:0]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
OCR
BLF
CLF
HCR
Reset
00000000
Access
R/W
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