參數(shù)資料
型號: ISP1563BM
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù): 53/102頁
文件大小: 466K
代理商: ISP1563BM
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
54 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
[1]
The reserved bits should always be written with the reset value.
11.1.19 HcRhDescriptorA register
This register is the rst of two registers describing the characteristics of the root hub.
Reset values are implementation-specic.
Table 79 shows the bit allocation of the HcRhDescriptorA register.
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
LST[11:8]
Reset
00000110
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
LST[7:0]
Reset
00101000
Access
R/W
Table 78.
HcLSThreshold - Host Controller Low-Speed Threshold register bit description
Address: Content of the base address register + 44h
Bit
Symbol
Description
31 to 12
reserved
-
11 to 0
LST[11:0]
LS Threshold: This eld contains a value that is compared to the FR[13:0] eld, before initiating a
low-speed transaction. The transaction is started only if FR
≥ this eld. The value is calculated by
the HCD, considering the transmission and set-up overhead.
Table 79.
HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit allocation
Address: Content of the base address register + 48h
Bit
31
30
29
28
27
26
25
24
Symbol
POTPGT[7:0]
Reset
11111111
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
NOCP
OCPM
DT
NPS
PSM
Reset
00001001
Access
R/W
R
R/W
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