參數(shù)資料
型號(hào)： ISP1563BM
廠商： ST-ERICSSON
元件分類(lèi)： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁(yè)數(shù)： 25/102頁(yè)
文件大?。?/td> 466K
代理商： ISP1563BM
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
29 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
The logic level of the AMB4 pin at power-on determines the default value of PMC
registers. If this pin is pulled up to 3.3 V, the ISP1563 will report that it supports PME
generation in D3cold (bit 15 (PME_S4) will be set to 1). If this pin is left open or is pulled
down, the ISP1563 will report that it does not support PME generation in D3cold (bit 15
(PME_S4) will be reset to 0).
8.2.3.4
PMCSR register
The Power Management Control/Status (PMCSR) register is a 2-byte register used to
manage the power management state of the PCI function, as well as to allow and monitor
Power Management Events (PMEs). The bit allocation of the register is given in Table 36.
[1]
Sticky bit, if the function supports PME# from D3cold, then X is indeterminate at the time of initial operating system boot; X is 0 if the
function does not support PME# from D3cold.
[2]
The reserved bits should always be written with the reset value.
Table 36.
PMCSR - Power Management Control/Status register bit allocation
Address: Value read from address 34h + 4h
Bit
15
14
13
12
11
10
9
8
Symbol
PMES
DS[1:0]
D_S[3:0]
PMEE
Reset
000000
Access
R/W
R
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[2]
PS[1:0]
Reset
00000000
Access
R/W
Table 37.
PMCSR - Power Management Control/Status register bit description
Address: Value read from address 34h + 4h
Bit
Symbol
Description
15
PMES
PME Status: This bit is set when the function normally assert the PME# signal independent of the
state of the PMEE bit. Writing logic 1 to this bit clears it and causes the function to stop asserting
PME#, if enabled. Writing logic 0 has no effect. This bit defaults to logic 0, if the function does not
support the PME# generation from D3cold. If the function supports the PME# generation from D3cold,
then this bit is sticky and must be explicitly cleared by the operating system each time the operating
system is initially loaded.
14 to 13
DS[1:0]
Data Scale: This two-bit read-only eld indicates the scaling factor when interpreting the value of the
Data register. The value and meaning of this eld vary, depending on which data value is selected by
the D_S eld. This eld is a required component of the Data register (offset 7) and must be
implemented, if the Data register is implemented. If the Data register is not implemented, this eld
must return 00b when PMCSR is read.
12 to 9
D_S[3:0]
Data Select: This four-bit eld selects the data that is reported through the Data register and the
D_S eld. This eld is a required component of the Data register (offset 7) and must be
implemented, if the Data register is implemented. If the Data register is not implemented, this eld
must return 00b when PMCSR is read.
8
PMEE
PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, PME# assertion is
disabled. This bit defaults to logic 0, if the function does not support the PME# generation from
D3cold. If the function supports PME# from D3cold, then this bit is sticky and must explicitly be cleared
by the operating system each time the operating system is initially loaded.
7 to 2
reserved
-
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