參數(shù)資料
型號: ISP1563BM
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù): 21/102頁
文件大小: 466K
代理商: ISP1563BM
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
25 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
8.2.2 Enhanced Host Controller-specic PCI registers
In addition to the PCI conguration header registers, EHCI needs some additional PCI
conguration space registers to indicate the serial bus release number, downstream port
wake-up event capability, and adjust the USB bus frame length for Start-Of-Frame (SOF).
The EHCI-specic PCI registers are given in Table 25.
8.2.2.1
SBRN register
The Serial Bus Release Number (SBRN) register is a 1-byte register, and the bit
description is given in Table 26. This register contains the release number of the USB
specication with which this USB Host Controller module is compliant.
8.2.2.2
FLADJ register
This feature is used to adjust any offset from the clock source that generates the clock that
drives the SOF counter. When a new value is written to these six bits, the length of the
frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is
given in Table 27.
[1]
The reserved bits should always be written with the reset value.
Table 25.
EHCI-specic PCI registers
Offset
Register
60h
Serial Bus Release Number (SBRN)
61h
Frame Length Adjustment (FLADJ)
62h to 63h
Port Wake Capability (PORTWAKECAP)
Table 26.
SBRN - Serial Bus Release Number register (address 60h) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
SBRN[7:0]
R
20h*
Serial Bus Specication Release Number: This register value is to identify
Universal Serial Bus Specication Rev. 2.0. All other combinations are reserved.
Table 27.
FLADJ - Frame Length Adjustment register (address 61h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
FLADJ[5:0]
Reset
00100000
Access
R/W
Table 28.
FLADJ - Frame Length Adjustment register (address 61h) bit description
Bit
Symbol
Description
7 to 6
reserved
-
5 to 0
FLADJ[5:0]
Frame Length Timing Value: Each decimal value change to this register corresponds to 16
high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a
SOF microframe length) is equal to 59488 + value in this eld. The default value is decimal 32
(20h), which gives a SOF cycle time of 60000, see Table 29.
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