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參數資料
| 型號： | IS42G32256-8PQ |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM |
| 中文描述： | 512K X 32 SYNCHRONOUS GRAPHICS RAM, 6.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM , PLASTIC, QFP-100 |
| 文件頁數： | 32/52頁 |
| 文件大?。?/td> | 456K |
| 代理商： | IS42G32256-8PQ |
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IS42G32256
32
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR037-0C
09/10/98
ISSI
Figure 21. Operating Frequency / Latency Relationships
Symbol Parameter
CL
t
CK
Clock Cycle Time
—
Operating Frequency
t
CAC
CAS
Latency
t
RCD
Active Command to Read/Write Command Delay Time
t
RAC
RAS
Latency (t
RCD
+ t
CAC
)
t
RC
Command Period (REF to REF/ACT to ACT)
t
RAS
Command Period (ACT to PRE)
t
RP
Command Period (PRE to ACT)
t
RRD
Command Period (ACT[0] to ACT [1])
t
CCD
Column Command Delay Time
(READ, READA, WRIT, WRITA)
t
DPL
Last Data In to Precharge Command Delay Time
t
DAL
Last Data In to Active/Refresh Command Delay Time
(Auto-Precharge, Same Bank)
t
RBD
Burst Stop Command to Output in
HIGH-Z Delay Time (Read)
t
WBD
Burst Stop Command to Input in Invalid Delay Time (Write) 0
t
RQL
Precharge Command to Output in
HIGH-Z Delay Time (Read)
t
WDL
Precharge Command to Input in Invalid Delay Time (Write) 0
t
BDAL
Block Write to Active Command
(Auto Precharge, Same Bank)
t
EP
Last Data Out to Precharge Command
t
SMCD
Special Mode Register Set to Command
t
RR
Register Set Command to Register Set Command
t
PQL
Last Output to Auto-Precharge Start Time (Read)
t
QMD
DQM to Output Delay Time (Read)
t
DMD
DQM to Input Delay Time (Write)
t
MCD
Mode Register Set to Command Delay Time
-7
-8
-10
Units
3
7
2
3
8
2
3
2
10
12
83
2
2
4
6
4
2
2
1
10
100
3
3
6
9
6
3
2
1
15
66
2
2
4
6
4
2
3
1
ns
MHz
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
143 100
3
3
6
9
6
3
2
1
125
3
3
6
9
6
3
3
1
2
2
4
6
4
2
2
1
2
5
2
4
2
5
2
4
2
5
2
4
cycle
cycle
3
2
3
2
3
2
cycle
0
2
0
3
0
2
0
3
0
2
cycle
cycle
3
0
5
0
6
0
5
0
6
0
5
cycle
cycle
6
–2
1
2
–2
2
0
1
–1
1
2
–1
2
0
1
–2
1
2
–2
2
0
1
–1
1
2
–1
2
0
1
–2
1
2
–2
2
0
1
–1
1
2
–1
2
0
1
cycle
cycle
cycle
cycle
cycle
cycle
cycle
相關PDF資料 |
PDF描述 |
|---|---|
| IS42G32256 | 256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM |
| IS42S16100C1 | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16100C1-5T | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16100C1-5TL | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16100C1-6T | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS42K | 制造商:IDEC Corporation 功能描述:SENS.IND. 10-30VDC NPN NC |
| IS42KS | 制造商:IDEC Corporation 功能描述:SENS.IND. 10-30VDC NPN NC |
| IS42L | 制造商:IDEC Corporation 功能描述:SENS.IND. 10-30VDC NPN NC |
| IS42LS16800A | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS16800A-10B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
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