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| 型號： | IS42G32256-8PQ |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM |
| 中文描述： | 512K X 32 SYNCHRONOUS GRAPHICS RAM, 6.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM , PLASTIC, QFP-100 |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 456K |
| 代理商： | IS42G32256-8PQ |
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IS42G32256
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR037-0C
09/10/98
21
ISSI
Table 11. About Burst Type Control
Basic Mode
Sequential Counting
At MRS, A3=“0”. See the Burst Sequence Table. (BL=4, 8)
BL=1, 2, 4, 8 and full page wrap around.
At MRS A3=“1”. See the Burst Sequence Table. (BL=4, 8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
At MRS A3=“1”. (See to interleave Counting Mode)
Staring Address LSB 3 bits A 0-2 should be “000” or “111”. @BL=8
— if LSB =“000”: Increment Counting.
— if LSB =“111”: Decrement Counting.
For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8)
— @ write, LSB =“000”, Accessed Column in order 0-1-2-3-4-5-6-7
— @ read, LSB =“111”, Accessed Column in order 7-6-5-4-3-2-1-0
At BL=4, same applications are possible. As above example, at
interleave Counting mode, by confining starting address to some
value, Pseudo-Decrement Counting Mode can be realize. See the
Burst Sequence Table carefully.
At MRS A3=“0”. (See to Sequential Counting Mode) A0-2 =“111”.
(See to Full Page Mode). Using Full Page Mode and Burst Stop
Command, Binary Counting Mode can be realized.
— @ Sequential Counting, Accessed Column in order
3-4-5-6-7-1-2-3 (BL=8)
— @ Pseudo-Binary Counting
Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command)
Note:
The next column address of 256 is 0.
Every cycle Read/Write Command with random column address can
realize Random Column Access. That is similar to Extended Data
Out (EDO) Operation of conventional DRAM.
Interleave Counting
Pseudo-Mode
Pseudo-Document
Sequential Counting
Pseudo-Binary Counting
Random Mode
Random Column
Access, t
CCD
= 1 CLK
Table 12. About Burst Length Control
Basic Mode
1
At MRS A2, 1, 0 = “000”. At auto precharge, t
RAS
should not be
violated.
At MRS A2, 1, 0 = “001”. At auto precharge, t
RAS
should not be
violated.
At MRS A2, 1, 0 =“010”.
At MRS A2, 1, 0 =“011”.
At MRS A2, 1, 0 =“111”. Wrap around mode (infinite burst length)
should be stopped by burst stop.
RAS
interrupt or
CAS
interrupt.
At MRS A9 =“1”. Read Burst =1, 2, 4, 8, full page/write Burst =1. At
auto precharge of write, t
RAS
should not be violated.
8-Column Block Write. LSB A0-2 are ignored. Burst length =1.
t
RAS
should not be violated. At auto precharge, t
RAS
should not be
violated.
t
BDL
=1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively.
Using burst stop command, random mode it is possible only at full
page burst length.
Before the end of burst, Row precharge command of the same bank
stops read/write burst with Row precharge. t
RDL
=1 with DQM, valid
DQ after burst stop is 1, 2 for CL=2, 3 respectively. During read/write
burst with auto precharge,
RAS
interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts
new read/write burst or block write. During read write burst with auto
precharge,
CAS
interrupt can not be issued.
2
4
8
Full Page
Special Mode
BRSW
Block Write
Random Mode
Burst Stop
Interrupt Mode
RAS
Interrupt
CAS
Interrupts
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