參數(shù)資料
型號: IS42G32256-8PQ
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM
中文描述: 512K X 32 SYNCHRONOUS GRAPHICS RAM, 6.5 ns, PQFP100
封裝: 14 X 20 MM , PLASTIC, QFP-100
文件頁數(shù): 15/52頁
文件大?。?/td> 456K
代理商: IS42G32256-8PQ
IS42G32256
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR037-0C
09/10/98
15
ISSI
Figure 6.
CAS
Interrupt (I)
Notes
:
1. By “Interrpt”, it is possible to stop burst read/write by external before the end of burst.
By “
CAS
Interrupt”, to stop burst read/write by
CAS
access; read, write, and block write.
2. t
CCD
:
CAS
to
CAS
delay (=1CLK).
3. t
CDL
: Last data in to new column address delay (=1CLK).
4. Pixel: Pixel mask.
5. t
CC
: Clock cycle time.
6. t
BWC
: Block write minimum cycle time.
7. Other bank can be active or precharge.
COMMAND
CLK
ADD
DQ (CLOCK
LATENCY = 2)
DQ (CLOCK
LATENCY = 3)
t
CCD
(SEE NOTE 2)
1. READ INTERRUPTED BY READ (BURST LENGTH = 4) (SEE NOTE 1.)
RD
RD
A
B
QA0
QB0
QB1
QB2
QB3
QB1
QB2
QA0
QB0
QB3
COMMAND
CLK
ADD
DQ
t
CCD (NOTE 2)
A
2. WRITE INTERRUPTED BY (BLOCK) WRITE (BURST LENGTH = 2)
WR
WR
WR
BW
B
A
B
DA0
DB0
DB1
DC0
PIXEL
t
CCD (NOTE 2)
(NOTE 4)
t
CDL
(NOTE 3)
t
CDL
(NOTE 3
COMMAND
CLK
ADD
DQ
(NOTE 7)
4. BLOCK WRITE TO BLOCK WRITE
BW
NOP
BW
A
X
B
PIXEL
PIXEL
t
BWC
(NOTE 6)
DQ (CLOCK
LATENCY = 2)
DQ (CLOCK
LATENCY = 3)
t
CCD (NOTE 2)
A
3. WRITE INTERRUPTED BY READ (BURST LENGTH = 2)
WR
RD
B
DA0
DB0
DB1
DA0
DB0
DB1
CDL
(NOTE 3)
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IS42G32256 256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM
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