參數(shù)資料
型號: IS42G32256-8PQ
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM
中文描述: 512K X 32 SYNCHRONOUS GRAPHICS RAM, 6.5 ns, PQFP100
封裝: 14 X 20 MM , PLASTIC, QFP-100
文件頁數(shù): 23/52頁
文件大?。?/td> 456K
代理商: IS42G32256-8PQ
IS42G32256
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR037-0C
09/10/98
23
ISSI
Table 13. Mask Function Procedure (continued)
b.
Illustration
I/O (=DQ)
(1)
DQMi
Color Register
Before Block Write & DQ (Pixel data)
000
001
010
011
100
101
110
111
After Block Write
000
001
010
011
100
101
110
111
Note:
1. At normal write, ONE column is selected among columns decoded by A2-0 (000-111).
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
31
24
23
16
15
8
7
0
DQM3=0
Color3=Blue
DQM2=0
Color2=Green
DQM1=0
Color1=Yellow
DQM0= 1
Color0=Red
White DQ24=H
White DQ25=H
White DQ26=H
White DQ27=L
White DQ28=H
White DQ29=H
White DQ30=H
White DQ31=L
White DQ16=H
White DQ17=H
White DQ18=L
White DQ19=H
White DQ20=H
White DQ21=H
White DQ22=L
White DQ23=H
White DQ8=H
White DQ9=L
White DQ10=H
White DQ11=H
White DQ12=H
White DQ13=L
White DQ14=H
White DQ15=H
White DQ0=L
White DQ1=H
White DQ2=H
White DQ3=H
White DQ4=L
White DQ5=H
White DQ6=H
White DQ7=H
Blue
Blue
Blue
White
Blue
Blue
Blue
White
Green
Green
White
Green
Green
Green
White
Green
Yellow
White
Yellow
Yellow
Yellow
White
Yellow
Yellow
White
White
White
White
White
White
White
White
3.
Pixel and I/O masking:By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See Pixel To DQ Mapping Table.
Assume 8bpp,
White = “0000, 0000”, Red = “1010, 0011”, Green = “1110, 0001”, Yellow = “0000, 1111”, Blue = ‘ 1100, 0011"
a.
STEP
I.
SMRS(LCR): Load color (for 8bpp, through x 32 DQ color0-3 are loaded into color registers)
Load (color3, color2, color1, color0, ) = (Blue, Green, Yellow, Red)
=“1100, 0011, 1110, 0001, 0000, 1111, 1010, 0011"
II.
SMRS(LMR) Load mask. Mask[31-0] = “1111, 1111, 1101, 1101, 0100, 0010, 0111, 0110”
Byte 3 : No I/O Masking ; Byte 2: I/O Masking ; Byte 1: I/O and Pixel Masking ; Byte 0: DQM Byte Masking
III. Row Active with DSF “H” : I/O mask by Write Per Bit Mode Enable
IV. Block Write with DQ [31-0] = “0111, 0111,1111, 1111, 0101, 0101, 1110, 1110” (Pixel Mask)
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