- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67684 > IBM37RGB524CF17A 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 PDF資料下載
參數(shù)資料
| 型號(hào)： | IBM37RGB524CF17A |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 8/72頁 |
| 文件大?。?/td> | 509K |
| 代理商： | IBM37RGB524CF17A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
10
March 17, 1995
RGB524
IBM
3.0
Modes of Operation
Pixel data can come from the VGA port or the VRAM
pixel port, as selected by the PORT SEL bit of the Mis-
cellaneous Control 2 register.
If the VRAM pixel port is selected, the pixel format can
be 4 BPP (bits per pixel), 8 BPP, 15/16 BPP, 24 BPP
Packed, or 32 BPP, selected by the Format bits of the
Pixel Format register. Table 7, “Pixel Format Table,” on
page 15 shows how the input bits are selected as a func-
tion of Pixel Format.
VGA data and 4 BPP data are always used to indirectly
generate 24 bits of color by indexing into the 256 entry
palettes. The Pixel Mask register is used to selectively
mask off the index bits as desired.
8 BPP, 15/16 BPP, 24 BPP Packed, and 32 BPP from the
VRAM pixel port can either be indirect (through the pal-
ettes) or direct (bypassing the palettes).
Each of these formats has an associated control register
with bits to select indirect or direct color. Additionally
15/16 BPP and 32 BPP formats allow a bit within the
incoming data to dynamically select indirect or direct
color.
As with VGA and 4 BPP, the Pixel Mask is used to mask
off palette address bits with indirect color access for 8,
15/16, 24 Packed, and 32 BPP.
3.1
Bit Ordering
Bit order is high-to-low. For 8 BPP, the MSB is ‘7’ and
the LSB is ‘0’; for 16 BPP the MSB is ‘15’ and the LSB is
‘0’, and so on.
When the VRAM pixel port is selected the default condi-
tion is to access the pixels from low to high. For each
LCLK, the rst pixel used is at the end with bit PIX[00],
and the last pixel used is at the end with bit PIX[63] (bit
PIX[31] for VRAM width = 32). For example, for 8 BPP,
the rst pixel is PIX[07:00], the second pixel is
PIX[15:08], and so on.
4 BPP is a special case. Within a byte, the default condi-
tion is to select rst the high nibble (e.g., PIX[07:04]),
then the low nibble (PIX[03:00]). The SWAP NIB bit of
the Miscellaneous Control 3 register may be used to
swap the order the two nibbles are used. This swap is
applied to every byte that is read in, and is only active,
when set, for 4 BPP.
3.2
VGA Port
VGA uses 8 bits per pixel. When the VGA port is
selected only indirect mode is used. The 8 bits are
masked with the Pixel Mask register and presented to
the red, green, and blue palettes as indices into the 256
entries of each palette. The masked data is used as the
same index into each of the three color palettes.
3.3
VRAM Pixel Port
3.3.1
4 BPP
With 4 BPP format 8 pixels (32 bit VRAM width) or 16
pixels (64 bit VRAM width) are obtained for each pixel
port data access. As noted above the default access of the
two pixels within each byte are high-to-low:
PIX[7:4] = pixel one
PIX[3:0] = pixel two,
but this can be reversed with the SWAP NIB bit of the
Miscellaneous Control 3 register.
4 BPP is only used in indirect color mode. The 4 bits are
masked with the 4 low order bits [3:0] of the Pixel Mask.
The resultant masked 4 bits are then used to index into
each of the red, green, and blue palettes.
With 4 BPP the 256 entry palettes are divided into 16
partitions of 16 entries per partition. The upper 4 bits of
the Pixel Mask register are ignored. The PARTITION
bits of the Palette Control register are used as the upper
4 bits of the palette address to select the desired parti-
tion. The 4 masked pixel bits are used to index to 1-of-16
entries within the selected partition.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC-WT-SO16N | ROTARY/LINEAR OPTICAL POSITION ENCODER |
| ICD2028SCR-5 | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20 |
| ICD2063SC-1 | 135 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICD2063SC-2 | 135 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICD2063SC-3 | 135 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM37RGB524CF22A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM39ENV422DLL00C | 制造商:IBM 功能描述: |
| IBM39ENV422PBA17C | 制造商:IBM Microelectronics 功能描述:VID ENCODER 420PIN HPBGA - Trays 制造商:IBM 功能描述:IBM IBM39ENV422PBA17C Encoders - Decoders |
| IBM39MPEGCD20PFD22C | 制造商:IBM 功能描述: |
| IBM39MPEGCS22PFJ22C | 制造商:IBM 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。