- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67684 > IBM37RGB524CF17A 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | IBM37RGB524CF17A |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 15/72頁 |
| 文件大?。?/td> | 509K |
| 代理商： | IBM37RGB524CF17A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
16
March 17, 1995
RGB524
IBM
4.0
Controls
4.1
Blank and Border Control
The BLANK and BORDER/OE signals control the way
in which data is presented to the DACs. These control
signals are used to determine when pixel data is valid,
when the border color is to be displayed, where the cur-
sor should be located on the screen, and how the MISR
will accumulate its signature.
4.2
Blanking Control
BLANK is latched by the rising edge of LCLK. When
BLANK is active (low), the data presented to the DACs
is forced to zeroes. When BLANK is inactive (high), the
pixel data or VGA data is considered valid (unless BOR-
DER is active), and the data is presented to the DACs as
determined by the current mode of operation. Cursor
data will override pixel data when the cursor is to be dis-
played.
4.3
Vertical Blanking
When BLANK is active (low) an internal counter is used
to determine whether or not the current blanking inter-
val is vertical blanking. If the counter reaches its maxi-
mum count of 2048 pixels, an internal signal will
become active to indicate that the end of the current
frame has been reached. This internal signal will
remain active until BLANK becomes inactive (high).
This vertical blanking detection is used by the cursor
logic to position the cursor (if enabled) in the following
frame. It is also used by the MISR (if enabled) to control
the accumulation of a signature for one complete frame
of pixel data.
4.4
Border Control
BORDER/OE is a shared function input. It can indicate
either “Border” time, for displaying a border, or
“Odd/Even” for use with interlace mode. The usage of
this pin is determined by the BRDR/INTL of the Miscel-
laneous Control 2 register. When used as a border con-
trol interlace mode is not supported with display of the
hardware cursor.
When used as BORDER, the input is latched by the ris-
ing edge of LCLK. When BLANK is active (low), BOR-
DER must also be active (low). When BLANK is inactive
(high), the state of BORDER will determine whether or
not the color in the Border Color registers is displayed.
If BORDER is active (low), the border color is displayed,
and if BORDER is inactive (high), the pixel data or cur-
sor data is displayed. For cursor positioning, the active
display area is considered valid when BORDER and
BLANK are both inactive (high). The MISR signature is
accumulated when BLANK alone is inactive (high), thus
the border area is included in the MISR accumulation. If
no border is required, the BORDER input should be tied
to BLANK.
The intent of the BORDER signal is to create a “picture
frame” around the active display area. BORDER can
remain active (low) for entire scan lines at the top and
bottom of the active display area, or it can be active at
the beginning and end of each scan line to create this
effect. Other changes in the BORDER signal within the
active display area are not allowed.
If the BRDR/INTL bit in Miscellaneous Control 2 is set
to “INTL” operation, no border will be displayed.
4.5
Sync Control
Three sync signals are brought into the device on two
pins, HCSYNCIN and VSYNCIN.
Four registers control what is done with these signals:
u
Sync Control (index 0x0003)
u
Horizontal Sync Position (index 0x0004)
u
DAC Operation (index 0x0006)
u
Power Management (index 0x0005)
Horizontal sync on HCSYNCIN is processed and sent
out on HSYNCOUT. Vertical sync on VSYNCIN is pro-
cessed and sent out on VSYNCOUT.
The intent of processing horizontal sync is to delay it to
match the delay seen by the pixel data from the inputs
(VGA[7:0] or PIX[63:0]) to the DAC outputs. In addition,
the signal may be inverted, forced low or high, or 3-
stated.
A mismatch between pixel delay and horizontal sync
delay can cause a visible effect, that is, the display may
not be centered horizontally on the screen. The vertical
display timings are generally such that mismatches are
not visible. Vertical sync is brought in on VSYNCIN and
sent out on VSYNCOUT to provide the same invert,
force low or high, and 3-state controls as provided for
horizontal sync.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC-WT-SO16N | ROTARY/LINEAR OPTICAL POSITION ENCODER |
| ICD2028SCR-5 | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20 |
| ICD2063SC-1 | 135 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICD2063SC-2 | 135 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICD2063SC-3 | 135 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM37RGB524CF22A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM39ENV422DLL00C | 制造商:IBM 功能描述: |
| IBM39ENV422PBA17C | 制造商:IBM Microelectronics 功能描述:VID ENCODER 420PIN HPBGA - Trays 制造商:IBM 功能描述:IBM IBM39ENV422PBA17C Encoders - Decoders |
| IBM39MPEGCD20PFD22C | 制造商:IBM 功能描述: |
| IBM39MPEGCS22PFJ22C | 制造商:IBM 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。