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參數(shù)資料
| 型號(hào)： | IBM37RGB524CF17A |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 5/72頁 |
| 文件大?。?/td> | 509K |
| 代理商： | IBM37RGB524CF17A |
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March 17, 1995
7
IBM
RGB524
2.9
PLL Frequency Selection
The REF DIV COUNT, VCO DIV COUNT, and DF bits
are provided to the PLLs in a pair of 8-bit registers. REF
DIV COUNT is 5 bits and occupies one register, with the
3 high order bits unused. The 6 VCO DIV COUNT bits
occupy the second register, with the 2 high order bits
used by DF.
For the SYSCLK PLL, the two programming registers
are the System PLL Reference Frequency, which holds
REF DIV COUNT, and the System PLL VCO Divider,
which holds VCO DIV COUNT and the DF bits.
For the pixel PLL, there are actually 17 registers which
can be used to hold the programming values: Fixed Pixel
PLL Reference Divider and F0 - F15. A pair of registers
is selected from this group to provide the pixel PLL pro-
gramming values. This selection is controlled by the
pixel PLL Control 1 and pixel PLL Control 2 registers.
Two different programming styles are supported:
Direct Programming In this scheme only the
register holding VCO DIV COUNT and DF is
altered to change the frequencies. The register
for REF DIV COUNT holds a value that is
constant for all frequencies. This method is
discussed in more detail below.
M over N In this scheme both register values are
changed to program a new frequency. The name
refers to the general PLL concept in which
Output frequency = Input reference
× (M/N)
where VCO DIV COUNT serves as M and REF
DIV COUNT serves as N, with modications to
the equation as shown in Table 3, "PLL
For the SYSCLK PLL there is not much distinction
between the two programming styles. Both registers are
written to provide an initial operating frequency. Then
to change frequency either one register is changed (Sys-
tem PLL VCO Divider), or both registers are changed,
depending on the programming style.
For the pixel PLL, a set of preprogrammed frequencies
can be stored in the F0 - F15 registers, and the number
of stored frequencies depends on the programming style.
When the direct programming style is used a single REF
DIV COUNT is stored in the Fixed PLL Reference
Divider register. Up to 16 values of VCO DIV COUNT
and DF can be stored in the F0 - F15 registers, allowing
16 preprogrammed pixel clock frequencies.
With the M/N style the Fixed Pixel PLL Reference
Divider register is not used. The F0 - F15 are recong-
ured as 8 pairs of M and N values (M0,N0,M1,N1,
…
M7,N7). This allows 8 preprogrammed pixel clock fre-
quencies.
The selection of the programming registers, either 1 of
the 16 F0 - F15 registers or 1 of the 8 M/N pairs, is done
either externally with the FS[1:0] inputs to the module,
or internally with the INT FS[3:0] bits of Pixel PLL Con-
trol 2 register. When the M/N style is used INT FS[3] is
ignored.
The programming style and selection source is chosen
with the EXT/INT bits of the Pixel PLL Control 1 regis-
ter, as shown in Table 4, "Pixel PLL Control 1 EXT/INT
Note that there are more selections available with the
internal register INT FS[3:0} than using the external
FS[1:0] inputs. With the external inputs, only 4 frequen-
cies can be chosen, using either direct programming or
M/N. With the INT FS[3:0} bits 8 frequencies can be cho-
sen using M/N or 16 frequencies can be chosen using
direct programming.
Table 4. Pixel PLL Control 1 EXT/INT Freq. Selection
EXT
/INT
Frequency
Selection
REF DIV
COUNT
VCO DIV
COUNT, DF
000
External
FS[1:0]
Fixed Reference
Divider
F0-F3
001
External
FS[1:0]
N0-N3
M0-M3
010
Internal
FS[3:0]
Fixed Reference
Divider
F0-F15
011
Internal
FS[2:0]
N0-N7
M0-M7
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