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參數資料
| 型號： | IBM37RGB524CF17A |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數： | 3/72頁 |
| 文件大?。?/td> | 509K |
| 代理商： | IBM37RGB524CF17A |
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March 17, 1995
5
IBM
RGB524
2.6
Additional Clocks
2.6.1
Load Clock
The LCLK input (Load Clock) is used to latch up all
incoming pixel data and video controls. The maximum
frequency of this input is 100 MHz.
2.6.2
Pixel Clock (Dot Clock)
The pixel clock, or dot clock, is the internal clock used to
clock pixel data up through the DACs. It is also required
to be running to access the palette and the cursor. The
maximum frequency of this clock is 170/220 MHz
(depending on the chip version).
There are several sources of the pixel clock, as selected
by the PCLK SEL bits in the Miscellaneous Control 2
register:
LCLK input This is the reset default. It is intended
to be used when the VGA port is selected as the
pixel source.
Pixel PLL output This is intended to be used when
the VRAM pixel port is selected as the pixel
source. It provides the highest pixel clock
operation.
REFCLK input This is intended for laboratory
bringup.
When LCLK is selected as the pixel clock all internal
pixel operations are synchronous with LCLK. If the
pixel clock is sourced by the pixel PLL output or REF-
CLK, then the incoming pixels and video controls are
expected to be derived from SCLK. After latching the
signals with LCLK, the signals are clocked with an
internal SCLK, and then clocked with the internal pixel
clock. LCLK must maintain a specied relationship to
SCLK to achieve the internal transfer of the clocking
from LCLK to SCLK.
2.7
PLL Setup and Reset
2.7.1
Pixel PLL
The PLL is enabled for running at a programmed fre-
quency by setting the REF DIV COUNT, VCO DIV
COUNT, and DF bits (as described in the following sec-
tions), and then setting the PLL ENAB bit of the Miscel-
laneous Clock Control register.
When the PLL ENAB bit is 0 (off), the PLL will continue
to run but the frequency will not be determined by pro-
gramming values. The PLL will drive to its lowest fre-
quency of operation, in the range of 5 KHz to 250 KHz.
The pixel clock frequency is determined by the DF pro-
gramming bits. When DF = 00, the pixel clock is equal to
the PLL clock divided by 4 (1.25 KHz to 62.5 KHz).
When DF = 01 the pixel clock equals the PLL clock
divided by 2 (2.25 KHz to 125 KHz), and when DF = 10
or 11, the pixel clocks equals the PLL clock (5 KHz to
250 KHz.)
Following a reset, the PLL ENAB bit is off and the DF
bits of all programming registers are set to 00, so the
pixel clock will be PLL clock/4 = 1.25 KHz to 64.25 KHz.)
The PORT SEL bit of Miscellaneous Control 2 register
will be 0 (VGA port), which will cause the SCLK output
to be the same as the pixel clock (1.25 KHz to 64.25
KHz.) The DDOT DIV bits of the Miscellaneous Clock
Control register will be zero, which will cause DDOT-
CLK to also be the same frequency as the pixel clock.
2.7.2
SYSCLK PLL
The SYSCLK PLL is enabled with the SPLL ENAB bit
of the System Clock Control register. Unlike the pixel
PLL, following a reset, this ENAB bit will be set, and
the SYSCLK PLL will be running and driving the
SYSCLK driver. The output frequency will be (33/16)
×
REFCLK.
When the SPLL bit is 0 (disabled) the SYSCLK PLL will
run in the 5 KHz to 250 KHz range similar to the pixel
PLL. The frequency driven on the SYSCLK output will
be determined by the value of the DF bits in the System
PLL VCO Divider register), using the same divide fac-
tors as described above for the pixel PLL.
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