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參數(shù)資料
| 型號： | IBM37RGB524CF17A |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 10/72頁 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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12
March 17, 1995
RGB524
IBM
contiguous. For 555 format there are 8 partitions and 32
entries within each partition. For 565 format there are 4
partitions. All 64 entries in the green palette are
addressed. Only the lower 32 entries of the red and blue
palettes are used; the high 32 entries are not used.
For sparse addressing the low order bits are dependent
on the ZIB/LIN bit. This bit must be set to 0 (ZIB). This
will force the low order bits to zeros. If ZIB/LIN is 1
(LIN) then the values of the low order bits presented to
the palettes are undened.
For sparse addressing the low order Pixel Mask bits
have no effect.
For contiguous addressing the high order bits are
always supplied by the PARTITION bits and the high
order Pixel Mask bits have no effect.
As noted above for dynamic bypass mode the format is
forced to 555 mode and addressing is forced to be sparse
regardless of the setting of the SPR/CNT bit.
Direct Color: To expand the 5 or 6 bits of color from the
pixel data to 8 bits, the ZIB/LIN bit of the 16 BPP Con-
trol register species the generation of the low order 3 or
2 bits. If ZIB (Zero Intensity Black), the low order bits
are made 0. If LIN (Linear), the low order bits are made
equal to the high order bits. This causes the 5 or 6 bits to
expand to 8 bits in a linear fashion, with both zero scale
and full scale values used. With Zero Intensity Black,
full scale cannot be achieved.
As noted above for dynamic bypass mode the format is
forced to 555 mode and the low order ll is forced as ZIB,
regardless of the setting of the ZIB/LIN bit.
3.3.3.3 Dynamic Bypass
As described above the selection of “dynamic bypass”
mode forces the 555 format and uses the high order bit
of the incoming 16-bit pixels as a control bit to select, on
a pixel-by-pixel basis, the indirect (color lookup) or
direct (lookup bypass) path.
The meaning of this bit depends on the BY16 bit in the
16 BPP Control register. When BY16 = 0 the incoming
control bit forces the bypass. That is, when the control
bit is 1 the palette is bypassed (direct color), and when 0
the palette is not bypassed (indirect color).
When BY16 = 1 the meaning of the incoming control bit
is reversed; it now forces a lookup. That is, when the
control bit is 1 the palette is used (color lookup), but
when 0 the palette is bypassed (direct color).
3.3.4
24 BPP
24 BPP Packed can only be selected when the VRAM
width is 64 bits. If 24 BPP Packed format is selected
with the Pixel Format register, but the VRAM SIZE bit
in the Miscellaneous Control 1 register is set for 32 bits,
then the product operation is undened.
With 24 BPP Packed format each 64-bit pixel port data
access contains 2+2/3 pixels. Every 3 consecutive pixel
port data accesses (3
× 8 = 24 bytes) contains 8 pixels of
3 bytes each. The assignment of the bytes for each of the
three accesses is shown in Figure 2 on page 12. Each
byte contains 8 bits of red, green, or blue color. Color
access can be indirect or direct, and is selected with the
B24P DCOL bit of the 24 BPP Packed Control register.
For indirect color, the 8 bits of red, green, and blue are
each masked by the Pixel mask, and then presented to
the red, green, and blue palettes as indices into the 256
entries of each palette.
For direct color, the 8 bits of red, green, and blue are pre-
sented to the DACs.
Figure 2.
24 BPP Packed Pixel Input from VRAM
1st
B
G
GB
R
G
B
R
B
BR
G
B
R
G
R
RG
B
R
G
B
Pixel 2
Pixel 1
Pixel 0
Pixel 5
Pixel 4
Pixel 3
Pixel 2
ACCESS
2nd
ACCESS
3rd
ACCESS
Pixel 7
Pixel 6
Pixel 5
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